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48 条记录 (耗时 0.024 秒)

    Novel conductor layout technique to reduce stress-induced void formations
    1.
    发明申请
    Novel conductor layout technique to reduce stress-induced void formations 有权
    新型导体布置技术，以减少应力引起的空隙形成

    公开(公告)号：US20070269907A1

    公开(公告)日：2007-11-22

    申请号：US11438127

    申请日：2006-05-22

    申请人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    发明人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    摘要翻译： 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

    Conductor layout technique to reduce stress-induced void formations
    2.
    发明授权
    Conductor layout technique to reduce stress-induced void formations 有权
    导体布置技术，以减少应力引起的空隙形成

    公开(公告)号：US08435802B2

    公开(公告)日：2013-05-07

    申请号：US11438127

    申请日：2006-05-22

    申请人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    发明人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    摘要翻译： 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

    Semiconductor device fault detection system and method
    4.
    发明申请
    Semiconductor device fault detection system and method 有权
    半导体器件故障检测系统及方法

    公开(公告)号：US20070096092A1

    公开(公告)日：2007-05-03

    申请号：US11264911

    申请日：2005-11-02

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    IPC分类号： H01L23/58

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

    摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。

    Test patterns for measurement of low-k dielectric cracking thresholds
    6.
    发明授权
    Test patterns for measurement of low-k dielectric cracking thresholds 失效
    用于测量低k电介质裂纹阈值的测试模式

    公开(公告)号：US06787803B1

    公开(公告)日：2004-09-07

    申请号：US10602970

    申请日：2003-06-24

    申请人： Chih-Hsiang Yao ,  Tai-Chun Huang

    发明人： Chih-Hsiang Yao ,  Tai-Chun Huang

    IPC分类号： H01L2166

    CPC分类号： H01L22/34

    摘要： The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).

    摘要翻译： 本发明提供了两个或更多个在测试图案（500,600,700,800）中使用以测定衬底上的电介质材料（104）的裂纹阈值的测试结构/子结构（100）。 每个测试结构/子结构（100）包括由介电材料（104）分开的两个金属结构（102），其宽度（G）对于每个测试结构/子结构（100）是不同的。 裂纹阈值将近似等于加工后破裂的电介质材料（104）的最大宽度（G）。 本发明还提供了一种用于确定介电材料（104）的裂纹阈值的方法。 在衬底（402）上形成两个或更多个测试结构（100），随后确定用于每个测试结构（100）的两个金属结构（102）之间的介电材料（104）是否在加工期间已经破裂（404） 。

    Semiconductor device fault detection system and method
    7.
    发明授权
    Semiconductor device fault detection system and method 有权
    半导体器件故障检测系统及方法

    公开(公告)号：US07791070B2

    公开(公告)日：2010-09-07

    申请号：US11264911

    申请日：2005-11-02

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    IPC分类号： G01R31/26

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

    摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。

    Integration film scheme for copper / low-k interconnect
    10.
    发明授权
    Integration film scheme for copper / low-k interconnect 有权
    铜/低k互连的集成电路方案

    公开(公告)号：US07244673B2

    公开(公告)日：2007-07-17

    申请号：US10706156

    申请日：2003-11-12

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    IPC分类号： H01L21/469

    CPC分类号： H01L23/53295 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.

    摘要翻译： 用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。 第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。 第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。 第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件 。