Invention Grant
- Patent Title: First inter-layer dielectric stack for non-volatile memory
- Patent Title (中): 用于非易失性存储器的第一层间介质叠层
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Application No.: US11697106Application Date: 2007-04-05
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Publication No.: US08435898B2Publication Date: 2013-05-07
- Inventor: Olubunmi O. Adetutu , Christopher B. Hundley , Paul A. Ingersoll , Craig T. Swift
- Applicant: Olubunmi O. Adetutu , Christopher B. Hundley , Paul A. Ingersoll , Craig T. Swift
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Hamilton & Terrile, LLP
- Agent Michael Rocco Cannatti
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.
Public/Granted literature
- US20080248649A1 First inter-layer dielectric stack for non-volatile memory Public/Granted day:2008-10-09
Information query
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