公开(公告)号：US08435898B2

公开(公告)日：2013-05-07

申请号：US11697106

申请日：2007-04-05

Applicant: Olubunmi O. Adetutu ,  Christopher B. Hundley ,  Paul A. Ingersoll ,  Craig T. Swift

Inventor： Olubunmi O. Adetutu ,  Christopher B. Hundley ,  Paul A. Ingersoll ,  Craig T. Swift

IPC: H01L21/4763

CPC classification number: H01L21/31612 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3221 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.

Abstract translation: 描述了一种用于形成具有基本均匀厚度的保护性吸气层（72）的第一层间电介质（ILD0）堆叠的方法和装置。 在衬底（31）上形成器件部件（32,33）之后，将SATEOS（52）的间隙填充电介质层沉积在PEN ESL（42）的蚀刻停止层上，然后在顺序沉积BPTEOS吸气层之前进行平坦化 （72）和在平坦化间隙填充介电层（52）上的覆盖电介质层（82）。 一旦形成了ILD0堆叠，就通过ILD0堆叠蚀刻一个或多个接触开口（92,94,96），从而将蚀刻停止层（42）暴露在预期的接触区域上。

公开(公告)号：US20110294292A1

公开(公告)日：2011-12-01

申请号：US12787296

申请日：2010-05-25

Applicant: Olubunmi O. Adetutu ,  Ted R. White ,  Mark D. Hall

Inventor： Olubunmi O. Adetutu ,  Ted R. White ,  Mark D. Hall

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76807 ,  H01L21/76808

Abstract: A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.

Abstract translation: 提供一种用于在具有对应于第一晶体管的栅电极和对应于第二晶体管的源/漏区的半导体器件中形成共用触点的方法。 该方法包括在覆盖栅电极和源极/漏极区的电介质层中形成第一开口，其中第一开口基本上延伸到对应于第一晶体管的栅电极。 该方法还包括在形成第一开口之后，在覆盖介质层中形成与第一开口邻接的第二开口，其中第二开口基本上延伸到对应于第二晶体管的源极/漏极区域。 该方法还包括通过用导电材料填充第一开口和第二开口来形成对应于第一晶体管的栅电极与对应于第二晶体管的源极/漏极区之间的共用接触。

公开(公告)号：US07811891B2

公开(公告)日：2010-10-12

申请号：US11331958

申请日：2006-01-13

Applicant: Marius K. Orlowski ,  Olubunmi O. Adetutu ,  Phillip J. Stout

Inventor： Marius K. Orlowski ,  Olubunmi O. Adetutu ,  Phillip J. Stout

IPC: H01L21/336

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.

Abstract translation: 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（36）上形成的栅极堆叠（30,32），由此形成具有垂直侧壁轮廓（35）的蚀刻栅极（33）。 通过用硅基层的分级材料组成构造栅极堆叠（30,32），其组成被选择以抵消预定的图案化和蚀刻步骤的蚀刻趋势，更理想的垂直栅极侧壁轮廓（ 35）。

公开(公告)号：US07704821B2

公开(公告)日：2010-04-27

申请号：US11146826

申请日：2005-06-07

Applicant: Dina H. Triyoso ,  Olubunmi O. Adetutu ,  Hsing H. Tseng

Inventor： Dina H. Triyoso ,  Olubunmi O. Adetutu ,  Hsing H. Tseng

IPC: H01L21/8238

CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.

Abstract translation: 用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。 形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。 沉积介电堆叠包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。 沉积一个电介质层包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。 沉积多个子层包括沉积无氮的子层并沉积含氮的子层。 沉积无氮子层包括用HfCl 4脉冲ALD室，用惰性气体冲洗室，用H 2 O或D 2 O脉冲室，并用惰性气体清洗室。

公开(公告)号：US20100081290A1

公开(公告)日：2010-04-01

申请号：US12241139

申请日：2008-09-30

Applicant: Tien Ying Luo ,  Olubunmi O. Adetutu

Inventor： Tien Ying Luo ,  Olubunmi O. Adetutu

IPC: H01L21/285

CPC classification number: H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

Abstract translation: 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

公开(公告)号：US20100035434A1

公开(公告)日：2010-02-11

申请号：US12579072

申请日：2009-10-14

Applicant: Dina H. Triyoso ,  Olubunmi O. Adetutu

Inventor： Dina H. Triyoso ,  Olubunmi O. Adetutu

IPC: H01L21/31 ,  H01L21/306

CPC classification number: H01L21/02315 ,  H01L21/02052 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/306 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.

Abstract translation: 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。

公开(公告)号：US07442621B2

公开(公告)日：2008-10-28

申请号：US10996319

申请日：2004-11-22

Applicant: Marius K. Orlowski ,  Mark C. Foisy ,  Olubunmi O. Adetutu

Inventor： Marius K. Orlowski ,  Mark C. Foisy ,  Olubunmi O. Adetutu

IPC: H01L21/76

CPC classification number: H01L29/7842 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878

Abstract: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Abstract translation: 半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。 在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。 衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。 可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。 可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。 因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

公开(公告)号：US07435646B2

公开(公告)日：2008-10-14

申请号：US11208670

申请日：2005-08-22

Applicant: Jeffrey W. Thomas ,  Olubunmi O. Adetutu

Inventor： Jeffrey W. Thomas ,  Olubunmi O. Adetutu

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.

Abstract translation: 半导体工艺和设备包括通过在半导体结构（10）上沉积氮化物层（20）来形成半导体器件，图案化和蚀刻氮化物层以形成图案化氮化物层（42,44），沉积多晶硅层 （62），用CMP工艺平坦化多晶硅层，以去除图案化的介电层（42,44）上方的多晶硅层（62）的任何部分，然后去除图案化的氮化物层（42,44），由此限定一个 或更多个可用作浮动栅极，晶体管栅极，位线或任何其它半导体器件特征的多晶硅特征（72,74,76）。

公开(公告)号：US07303983B2

公开(公告)日：2007-12-04

申请号：US11331763

申请日：2006-01-13

Applicant: Dina H. Triyoso ,  Olubunmi O. Adetutu ,  James K. Schaeffer

Inventor： Dina H. Triyoso ,  Olubunmi O. Adetutu ,  James K. Schaeffer

IPC: H01L21/3205

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.

Abstract translation: 一种半导体工艺和装置，通过在栅介质层（11）上形成第一导电层（22）制造金属栅电极，在第一导电层上形成过渡层（32），使用原子层沉积工艺，其中非晶化 随着形成过渡层，材料越来越多地加入，在过渡层上形成覆盖导电层（44），然后选择性地蚀刻覆盖导电层，过渡层和第一导电层，从而形成蚀刻栅叠层 （52）。 通过用原子层沉积工艺形成过渡层（32），其中非晶化材料（例如硅，碳或氮）越来越多地被加入，过渡层（32）被构造成具有较低的区域（例如，31， 33）和具有阻挡硅扩散的非晶结构的上部区域（例如，37,39）。

公开(公告)号：US07179700B2

公开(公告)日：2007-02-20

申请号：US10895553

申请日：2004-07-21

Applicant: Olubunmi O. Adetutu ,  William J. Taylor, Jr.

Inventor： Olubunmi O. Adetutu ,  William J. Taylor, Jr.

IPC: H01L21/8238

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/456

Abstract: An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to the P work function of 5.2 electron volts, and the N-type source/drain contacts of the N channel transistors have a silicide that is close to the N work function of 4.1 electron volts. This provides for a lower resistance at the interface between these source/drain contact regions and the corresponding silicide. These suicides with differing work functions are achieved with implants as needed. For example, for N-type source/drain contacts and a base metal of cobalt, titanium, or nickel, the implanted material is platinum and/or iridium. For the P-type, the implanted material is erbium, yttrium, dysprosium, gadolinium, hafnium, or holmium.

Abstract translation: N沟道晶体管和P沟道晶体管的源极/漏极接触不同的自杀，以提供低电阻触点。 选择硅化物以提供工作功能的良好匹配。 P沟道晶体管的P型源极/漏极触点具有接近5.2电子伏特的P功函数的硅化物，并且N沟道晶体管的N型源极/漏极触点具有接近于 4.1电子伏特的N工作功能。 这提供了在这些源极/漏极接触区域和相应的硅化物之间的界面处的较低电阻。 具有不同工作功能的这些自杀根据需要用植入物实现。 例如，对于N型源极/漏极触点和钴，钛或镍的母体金属，植入的材料是铂和/或铱。 对于P型，植入的材料是铒，钇，镝，钆，铪或钬。