公开(公告)号：US09136360B1

公开(公告)日：2015-09-15

申请号：US14297657

申请日：2014-06-06

申请人： Asanga H. Perera ,  Ko-Min Chang ,  Craig T. Swift

发明人： Asanga H. Perera ,  Ko-Min Chang ,  Craig T. Swift

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825

摘要： Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.

摘要翻译： 形成存储器结构包括在衬底上形成电荷存储层; 形成第一控制栅层; 图案化第一控制栅极层以在第一控制栅极层和电荷存储层中形成开口，其中开口延伸到基板中; 用绝缘材料填充开口; 在所述图案化的第一控制栅极层和绝缘材料上形成第二控制栅极层; 图案化第二控制栅极层以形成第一控制栅电极和第二控制栅电极，其中第一控制栅电极包括第一和第二控制栅层中的每一个的第一部分，而第二控制栅电极包括第二部分 并且所述绝缘材料位于所述控制栅电极之间; 以及在控制栅电极附近形成选择栅电极。

公开(公告)号：US07745870B2

公开(公告)日：2010-06-29

申请号：US11626681

申请日：2007-01-24

申请人： Gowrishankar L. Chindalore ,  Craig T. Swift

发明人： Gowrishankar L. Chindalore ,  Craig T. Swift

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。

公开(公告)号：US07592224B2

公开(公告)日：2009-09-22

申请号：US11393287

申请日：2006-03-30

申请人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Paul A. Ingersoll

发明人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Paul A. Ingersoll

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C16/0458 ,  G11C2216/06 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825

摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。

公开(公告)号：US20090170262A1

公开(公告)日：2009-07-02

申请号：US12397905

申请日：2009-03-04

申请人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Laureen H. Parker

发明人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Laureen H. Parker

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L27/11521 ,  Y10S438/926 ,  Y10S438/962

摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间​​的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。

公开(公告)号：US07285819B2

公开(公告)日：2007-10-23

申请号：US11188582

申请日：2005-07-25

申请人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

发明人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7923

摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

公开(公告)号：US20070020820A1

公开(公告)日：2007-01-25

申请号：US11188909

申请日：2005-07-25

申请人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

发明人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

IPC分类号： H01L21/8232

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C16/0475 ,  H01L27/11519 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/7885 ,  Y10S977/707 ,  Y10S977/712

摘要： A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can further include forming a first gate electrode within the trench, wherein a discontinuous storage element lies between the first gate electrode and a wall of the trench. The process can still further include removing a part of the second set of discontinuous storage elements and forming a second gate electrode over the first gate electrode. After forming the second gate electrode, substantially none of the second set of discontinuous storage elements lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.

公开(公告)号：US20070018240A1

公开(公告)日：2007-01-25

申请号：US11188910

申请日：2005-07-25

申请人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

发明人： Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

IPC分类号： H01L29/94

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  G11C16/0475 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  Y10S977/707 ,  Y10S977/712

摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

公开(公告)号：US06898129B2

公开(公告)日：2005-05-24

申请号：US10280294

申请日：2002-10-25

申请人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

发明人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

IPC分类号： G11C16/04 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0466

摘要： A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

摘要翻译： 非易失性存储器包括具有非导电存储介质的多个晶体管。 晶体管通过从晶体管的源极边缘区域和漏极边缘区域两端向存储介质注入空穴而被擦除。 在一个示例中，存储介质由从下面的衬底隔离并由二氧化硅覆盖的栅极制成。 在存储介质中注入孔产生具有重叠部分的两个孔分布。 重叠部分的组合分布高于存储介质的重叠区域中程序电荷的最高浓度的至少一个水平。 在一个示例中，通过热载流子注入对晶体管进行编程。 在一些示例中，解码存储器的晶体管组的源。

公开(公告)号：US06887758B2

公开(公告)日：2005-05-03

申请号：US10267153

申请日：2002-10-09

申请人： Gowrishankar L. Chindalore ,  Paul A. Ingersoll ,  Craig T. Swift ,  Alexander B. Hoefler

发明人： Gowrishankar L. Chindalore ,  Paul A. Ingersoll ,  Craig T. Swift ,  Alexander B. Hoefler

IPC分类号： H01L21/336 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.

摘要翻译： 半导体器件（10）具有均匀地注入到半导体衬底（20）中的具有第一导电类型的高掺杂层（26）。 氧化物 - 氧化物 - 氧化物结构（36,38,40）形成在半导体衬底（20）上。 具有第一导电类型的卤素区域（46）以仅在氧化物 - 氧化物 - 氧化物结构的漏极侧的角度被注入，并且在氧化物 - 氮化物 - 氧化物结构之下延伸到氧化氮化物 - 氮化物的边缘的预定距离 氧化物结构。 具有第二导电类型的源极（52）和漏极（54）被注入衬底（20）中。 所得的非易失性存储单元提供低的自然阈值电压，以在读周期期间最小化阈值电压漂移。 此外，在漏极侧使用卤素区域（46）允许更高的编程速度，并且高掺杂层（26）允许使用短通道器件。

公开(公告)号：US06751125B2

公开(公告)日：2004-06-15

申请号：US10287328

申请日：2002-11-04

申请人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

发明人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/26 ,  G11C16/3418

摘要： A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current. Accordingly, the voltage thresholds of transistors having an erased state can be reduced, wherein the read gate voltage can be reduced as well.

摘要翻译： 一种用于降低存储器阵列中的读栅极电压的技术，包括具有用于存储指示存储在单元中的值的电荷的晶体管的存储单元。 在一个示例中，大于衬底电压的电压被施加到阵列的存储器单元的晶体管的源极，以增加由于体效应引起的晶体管的阈值电压。 读栅极电压大于比基板电压大的源极电压。 小于源极电压的非读取电压被施加到未选择行的晶体管的栅极以减少泄漏电流。 利用本实施例，具有擦除状态的晶体管的阈值电压可以小于0V。 利用一些实施例，由于栅极电压的降低可以降低由栅极电压引起的读取干扰。 在其他示例中，负电压施加到未选择的行的栅极以防止漏电流。 因此，可以减少具有擦除状态的晶体管的电压阈值，其中读取栅极电压也可以减小。