发明授权
US08443310B2 Pattern correcting method, mask forming method, and method of manufacturing semiconductor device
有权
图案校正方法，掩模形成方法和制造半导体器件的方法
- 专利标题： Pattern correcting method, mask forming method, and method of manufacturing semiconductor device
- 专利标题（中）： 图案校正方法，掩模形成方法和制造半导体器件的方法
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申请号： US13237435申请日： 2011-09-20
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公开(公告)号： US08443310B2公开(公告)日： 2013-05-14
- 发明人: Masanari Kajiwara , Toshiya Kotani , Sachiko Kobayashi , Hiromitsu Mashita , Fumiharu Nakajima
- 申请人： Masanari Kajiwara , Toshiya Kotani , Sachiko Kobayashi , Hiromitsu Mashita , Fumiharu Nakajima
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2011-064318 20110323
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.
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