Invention Grant
- Patent Title: Chip stack package
- Patent Title (中): 芯片堆栈封装
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Application No.: US13224670Application Date: 2011-09-02
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Publication No.: US08446016B2Publication Date: 2013-05-21
- Inventor: Sun-Won Kang , Seung-Duk Baek , Jong-Joo Lee
- Applicant: Sun-Won Kang , Seung-Duk Baek , Jong-Joo Lee
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2007-0109698 20071030
- Main IPC: H01L23/538
- IPC: H01L23/538

Abstract:
A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.
Public/Granted literature
- US20110316159A1 CHIP STACK PACKAGE Public/Granted day:2011-12-29
Information query
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