Invention Grant
US08446191B2 Phase locked loop with digital compensation for analog integration
有权
具有数字补偿的锁相环,用于模拟集成
- Patent Title: Phase locked loop with digital compensation for analog integration
- Patent Title (中): 具有数字补偿的锁相环,用于模拟集成
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Application No.: US12632053Application Date: 2009-12-07
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Publication No.: US08446191B2Publication Date: 2013-05-21
- Inventor: Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri , Jifeng Geng , Gurkanwal S. Sahota
- Applicant: Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri , Jifeng Geng , Gurkanwal S. Sahota
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agent Eric Ho
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
Public/Granted literature
- US20110133794A1 PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION Public/Granted day:2011-06-09
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