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公开(公告)号：US08446191B2
公开(公告)日：2013-05-21
申请号：US12632053
申请日：2009-12-07
IPC分类号： H03L7/06
摘要： A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
摘要翻译： 锁相环（PLL）装置包括数字微分器，其被配置为区分数字环路信号以至少部分地补偿模拟积分器对模拟电流信号的积分。 数模转换器（DAC）包括基于数字输入信号产生模拟电流信号的电流源输出级。 模拟积分器对模拟电流信号进行积分，以产生用于控制压控振荡器（VCO）的电压控制信号。
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公开(公告)号：US20110133799A1
公开(公告)日：2011-06-09
申请号：US12632061
申请日：2009-12-07
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.
摘要翻译： 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。
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公开(公告)号：US08339165B2
公开(公告)日：2012-12-25
申请号：US12632061
申请日：2009-12-07
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.
摘要翻译： 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。
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4.发明授权公开(公告)号：US08076960B2
公开(公告)日：2011-12-13
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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公开(公告)号：US20110143689A1
公开(公告)日：2011-06-16
申请号：US12638822
申请日：2009-12-15
申请人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
发明人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译： 抽取第一周期信号以产生第二周期信号的技术。 在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。 使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。 在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。
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6.发明申请DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER 有权使用累加器和相数转换器进行两点调制的数字锁相环公开(公告)号：US20100277211A1
公开(公告)日：2010-11-04
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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公开(公告)号：US08098103B2
公开(公告)日：2012-01-17
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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公开(公告)号：US20100315169A1
公开(公告)日：2010-12-16
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/097
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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公开(公告)号：US08588720B2
公开(公告)日：2013-11-19
申请号：US12638822
申请日：2009-12-15
申请人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
发明人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译： 抽取第一周期信号以产生第二周期信号的技术。 在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。 使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。 在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。
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公开(公告)号：US20110158346A1
公开(公告)日：2011-06-30
申请号：US12649754
申请日：2009-12-30
申请人： Gary J. Ballantyne
发明人： Gary J. Ballantyne
CPC分类号： H04B1/525 , H04B1/0475 , H04J11/0023
摘要： A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.
摘要翻译： 描述发射机电路。 发射机电路包括产生等于双工频率的第一频率的第一本地振荡器。 发射机电路还包括产生等于接收频率的第二频率的第二本地振荡器。 发射机电路还包括将第一频率与第一输入信号组合的第一混频器。 发射机电路还包括第一反馈环路。 第一反馈回路包括将第二频率与发射信号和第一滤波器组合的第二混频器和将第一混频器的输出与第一滤波器的输出组合的第一加法器。 发射机电路还包括产生等于接收频率的第三频率的第三本地振荡器。 发射机电路还包括将第三频率与第一加法器的输出组合的第三混频器。
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