发明授权
- 专利标题: Semiconductor device and method for manufacturing the same
- 专利标题(中): 半导体装置及其制造方法
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申请号: US13024004申请日: 2011-02-09
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公开(公告)号: US08455925B2公开(公告)日: 2013-06-04
- 发明人: Masashige Moritoki , Takamasa Itou , Takashi Ogura , Tsutomu Himukai , Shigeaki Shimizu
- 申请人: Masashige Moritoki , Takamasa Itou , Takashi Ogura , Tsutomu Himukai , Shigeaki Shimizu
- 申请人地址: JP Kanagawa
- 专利权人: Renesas Electronic Coporation
- 当前专利权人: Renesas Electronic Coporation
- 当前专利权人地址: JP Kanagawa
- 代理机构: Young & Thompson
- 优先权: JP2010-027974 20100210
- 主分类号: H01L23/52
- IPC分类号: H01L23/52
摘要:
To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.