公开(公告)号：US08455925B2

公开(公告)日：2013-06-04

申请号：US13024004

申请日：2011-02-09

申请人： Masashige Moritoki ,  Takamasa Itou ,  Takashi Ogura ,  Tsutomu Himukai ,  Shigeaki Shimizu

发明人： Masashige Moritoki ,  Takamasa Itou ,  Takashi Ogura ,  Tsutomu Himukai ,  Shigeaki Shimizu

IPC分类号： H01L23/52

CPC分类号： H01L21/76895 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.

摘要翻译： 为了提供一种在抑制逻辑电路的接触电阻的增加的同时最大限度地实现存储电路的电容器电容的增加的半导体器件的结构及其制造方法。 当将具有构成逻辑电路区域的布线的局部互连层的层数指定为M并且指定具有构成存储器电路的布线的局部互连层的层数为N（M和N为自然数 并且满足M> N），在由（MN）层或（M-N + 1）层组成的互连层上提供电容元件。