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公开(公告)号：US08455925B2
公开(公告)日：2013-06-04
申请号：US13024004
申请日：2011-02-09
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.
摘要翻译： 为了提供一种在抑制逻辑电路的接触电阻的增加的同时最大限度地实现存储电路的电容器电容的增加的半导体器件的结构及其制造方法。 当将具有构成逻辑电路区域的布线的局部互连层的层数指定为M并且指定具有构成存储器电路的布线的局部互连层的层数为N（M和N为自然数 并且满足M> N），在由（MN）层或（M-N + 1）层组成的互连层上提供电容元件。
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公开(公告)号：US07786005B2
公开(公告)日：2010-08-31
申请号：US11369955
申请日：2006-03-08
申请人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
发明人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
IPC分类号： H01L21/467
CPC分类号： H01L21/02063 , H01L21/76814
摘要： An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
摘要翻译： 由于可以有效地防止在形成通孔之后形成和生长的改变层的存在而导致的通孔电阻的增加，从而提供了半导体器件的改进的可靠性。 一种方法包括：在半导体衬底上形成TiN膜; 在TiN膜的表面上形成层间绝缘膜; 在所述层间绝缘膜的表面上形成抗蚀剂膜; 蚀刻其上形成有抗蚀剂膜的半导体衬底以形成开口，从而部分地暴露TiN膜; 等离子体处理TiN膜的暴露部分以去除在TiN膜的暴露部分中形成的改变的层; 并通过高温等离子体处理剥离抗蚀剂膜。
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公开(公告)号：US20060214300A1
公开(公告)日：2006-09-28
申请号：US11369955
申请日：2006-03-08
申请人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
发明人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
IPC分类号： H01L23/52
CPC分类号： H01L21/02063 , H01L21/76814
摘要： An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
摘要翻译： 由于可以有效地防止在形成通孔之后形成和生长的改变层的存在而导致的通孔电阻的增加，从而提供了半导体器件的改进的可靠性。 一种方法包括：在半导体衬底上形成TiN膜; 在TiN膜的表面上形成层间绝缘膜; 在所述层间绝缘膜的表面上形成抗蚀剂膜; 蚀刻其上形成有抗蚀剂膜的半导体衬底以形成开口，从而部分地暴露TiN膜; 等离子体处理TiN膜的暴露部分以去除在TiN膜的暴露部分中形成的改变的层; 并通过高温等离子体处理剥离抗蚀剂膜。
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公开(公告)号：US07947568B2
公开(公告)日：2011-05-24
申请号：US12548471
申请日：2009-08-27
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device includes a process of forming a STI trench in a substrate, a process of forming a thermal oxide film on a sidewall and a bottom surface of the STI trench, a process of performing a plasma treatment on a surface of the thermal oxide film that is located at a bottom portion of the STI trench, and a process of forming an insulating film in the STI trench using a CVD method.
摘要翻译： 制造半导体器件的方法包括在衬底中形成STI沟槽的工艺，在STI沟槽的侧壁和底表面上形成热氧化膜的工艺，在表面上进行等离子体处理的工艺 位于STI沟槽的底部的热氧化膜，以及使用CVD法在STI沟槽中形成绝缘膜的工序。
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5.发明授权Manufacturing method of semiconductor device having self-aligned contact connected to silicide layer on substrate surface 有权具有与衬底表面上的硅化物层连接的自对准接触的半导体器件的制造方法公开(公告)号：US08143152B2
公开(公告)日：2012-03-27
申请号：US12503464
申请日：2009-07-15
申请人： Masashige Moritoki
发明人： Masashige Moritoki
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76832 , H01L29/66545
摘要： A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.
摘要翻译： 半导体器件100包括：硅衬底102; 第一栅极114a，其包括形成在硅衬底102上的栅电极108和形成在栅电极108的侧壁上的侧壁112; 在硅衬底102的表面上与第一栅极114a的侧壁112侧向形成的硅化物层132; 以及在平面图中至少部分地与第一栅极114a重叠并到达硅衬底102的表面的硅化物层132的触点164; 其中绝缘膜位于第一栅极114a的触头164和栅电极108之间。
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公开(公告)号：US20060065979A1
公开(公告)日：2006-03-30
申请号：US11235309
申请日：2005-09-27
IPC分类号： H01L23/52
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76814 , H01L21/76834 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which is excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug is provided with good production stability. The semiconductor device includes a semiconductor substrate, an insulating interlayer 101, and a multi-layer structure. The insulating interlayer 101 is formed in the upper portion of the semiconductor substrate. The multi-layer structure is provided on the insulating interlayer 101. A Ti film 105, a TiN film 107, an AlCu film 109, a Ti film 111, a TiN film 113, and an etching adjustment film 115 are sequentially formed in the multi-layer structure. The semiconductor device includes an insulating interlayer 103 and a conductive plug. The insulating interlayer 103 is provided on the insulating interlayer 101 and the multi-layer structure. The conductive plug penetrates the insulating interlayer 103 and the etching adjustment film 115, and an end surface of the conductive plug is located in the TiN film 113. The conductive plug includes a Ti film 117, a TiN film 119, and a W film 121.
摘要翻译： 在包含Al的金属膜上的抗反射膜与导电插塞之间的接触性优异的半导体器件具有良好的生产稳定性。 半导体器件包括半导体衬底，绝缘夹层101和多层结构。 绝缘中间层101形成在半导体衬底的上部。 多层结构设置在绝缘中间层101上。多层结构依次形成Ti膜105，TiN膜107，AlCu膜109，Ti膜111，TiN膜113和蚀刻调整膜115 层结构。 半导体器件包括绝缘夹层103和导电插塞。 绝缘中间层103设置在绝缘中间层101和多层结构上。 导电插塞穿过绝缘夹层103和蚀刻调整膜115，并且导电插塞的端面位于TiN膜113中。导电插塞包括Ti膜117，TiN膜119和W膜121 。
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公开(公告)号：US5759751A
公开(公告)日：1998-06-02
申请号：US795631
申请日：1997-02-06
申请人： Yuji Shimizu , Kohiro Ito , Masashige Moritoki
发明人： Yuji Shimizu , Kohiro Ito , Masashige Moritoki
IPC分类号： G03F7/32 , G03F7/40 , G03F7/42 , H01L21/02 , H01L21/027 , H01L21/304 , H01L21/306 , H01L21/3063 , H01L21/311 , H01L21/3213 , G03C5/00
CPC分类号： H01L21/02071 , G03F7/425 , H01L21/02063 , H01L21/31133
摘要： A semiconductor manufacturer peels a photo-resist mask off by using organic alkaline solvent, and the residual alkaline solvent is neutralized with acid before a rinse in pure water so as to prevent a metal wiring from erosion due to strong alkaline solution produced from the residual organic alkaline solvent.
摘要翻译： 半导体制造商通过使用有机碱性溶剂剥离光致抗蚀剂掩模，并且在纯水中冲洗之前用酸中和残留的碱性溶剂，以防止金属布线由于残留有机物产生的强碱性溶液而侵蚀 碱性溶剂。
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公开(公告)号：US07646096B2
公开(公告)日：2010-01-12
申请号：US11235309
申请日：2005-09-27
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76814 , H01L21/76834 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having good production stability and excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug. The device includes a substrate, an insulating interlayer, and a multi-layer structure. The insulating interlayer is formed in the upper portion of the substrate. The structure is provided on the insulating interlayer. A Ti film, a first TiN film, an AlCu film, a Ti film, a second TiN film, and an etching adjustment film are sequentially formed in the structure. The device includes an insulating interlayer and a conductive plug. The insulating interlayer is provided on the insulating interlayer and the structure. The conductive plug penetrates the insulating interlayer and the etching adjustment film, and an end surface of the conductive plug is located in the second TiN film. The conductive plug includes a Ti film, a TiN film, and a W film.
摘要翻译： 具有良好的生产稳定性和在包含Al的金属膜上的抗反射膜与导电插塞之间的接触性能优异的半导体器件。 该装置包括基板，绝缘夹层和多层结构。 绝缘中间层形成在基板的上部。 该结构设置在绝缘中间层上。 在该结构中依次形成Ti膜，第一TiN膜，AlCu膜，Ti膜，第二TiN膜和蚀刻调整膜。 该装置包括绝缘夹层和导电塞。 绝缘中间层设置在绝缘中间层和结构上。 导电插塞穿透绝缘中间层和蚀刻调整膜，并且导电插塞的端面位于第二TiN膜中。 导电插塞包括Ti膜，TiN膜和W膜。
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公开(公告)号：US20090087957A1
公开(公告)日：2009-04-02
申请号：US12232885
申请日：2008-09-25
申请人： Hiromi Sasaki , Masashige Moritoki
发明人： Hiromi Sasaki , Masashige Moritoki
IPC分类号： H01L21/02
CPC分类号： H01L21/31138 , H01L28/60
摘要： Photoresist on a metal is removed with less oxidation of the metal surface by the invented ashing. During process, the matching of oxygen gas ratio and wafer temperature under downstream plasma which means no RF bias plasma is controlled for oxidation amount not to depend on ashing time with required photo resist rate in manufacturing.
摘要翻译： 通过本发明的灰化，金属表面的氧化较少，金属上的光刻胶被去除。 在处理过程中，控制下游等离子体的氧气比和晶片温度的匹配，这意味着没有RF偏置等离子体的氧化量不依赖于制造时所需光刻胶的灰化时间。
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公开(公告)号：US07879680B2
公开(公告)日：2011-02-01
申请号：US12232885
申请日：2008-09-25
申请人： Hiromi Sasaki , Masashige Moritoki
发明人： Hiromi Sasaki , Masashige Moritoki
IPC分类号： H01L21/02
CPC分类号： H01L21/31138 , H01L28/60
摘要： Photoresist on a metal is removed with less oxidation of the metal surface by the invented ashing. During process, the matching of oxygen gas ratio and wafer temperature under downstream plasma which means no RF bias plasma is controlled for oxidation amount not to depend on ashing time with required photo resist rate in manufacturing.
摘要翻译： 通过本发明的灰化，金属表面的氧化较少，金属上的光刻胶被去除。 在处理过程中，控制下游等离子体的氧气比和晶片温度的匹配，这意味着没有RF偏置等离子体的氧化量不依赖于制造时所需光刻胶的灰化时间。
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