Invention Grant
- Patent Title: Methods and apparatus for thinning, testing and singulating a semiconductor wafer
- Patent Title (中): 减薄,测试和分割半导体晶片的方法和装置
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Application No.: US13292037Application Date: 2011-11-08
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Publication No.: US08461024B2Publication Date: 2013-06-11
- Inventor: Morgan T. Johnson
- Applicant: Morgan T. Johnson
- Applicant Address: US OR Beaverton
- Assignee: Advanced Inquiry Systems, Inc.
- Current Assignee: Advanced Inquiry Systems, Inc.
- Current Assignee Address: US OR Beaverton
- Agency: Perkins Coie LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.
Public/Granted literature
- US20120149134A1 METHODS AND APPARATUS FOR THINNING, TESTING AND SINGULATING A SEMICONDUCTOR WAFER Public/Granted day:2012-06-14
Information query
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