公开(公告)号：US07786724B1

公开(公告)日：2010-08-31

申请号：US12427748

申请日：2009-04-22

Applicant: Morgan T. Johnson ,  Lawrence H. Walls ,  Raymond J. Werner

Inventor： Morgan T. Johnson ,  Lawrence H. Walls ,  Raymond J. Werner

IPC: G01R31/02

CPC classification number: G01R31/2831 ,  G01R31/2894

Abstract: Collecting process characterization data local to a failed integrated circuit (IC), includes providing a wafer having ICs, each IC having contact terminals, the wafer having process characterization test sites distributed across it such that at least one process characterization test site is adjacent each IC; selecting two or more ICs for simultaneous testing; for each of those ICs, coupling two or more contact terminals of the selected IC, and a corresponding two or more contact terminals of an associated test site to corresponding input terminals of a multiplexer, each multiplexer having an output terminal and a select control input terminal, the multiplexer operable to selectively provide an electrical pathway between either an IC contact terminal or a test site contact terminal and the multiplexer output terminal; coupling the output terminal of each multiplexer to a tester channel; operating the multiplexer so that its output terminal is coupled to the IC contact terminal; simultaneously testing two or more ICs; detecting a failure of at least one of the selected ICs prior to completion of testing the remaining ICs simultaneously being tested; subsequent to detecting the failure, operating the multiplexer so that its output terminal is coupled to the test site contact terminal; and collecting process characterization data prior to completion of testing the remaining ICs.

Abstract translation: 收集故障集成电路（IC）局部的过程表征数据包括提供具有IC的晶片，每个IC都具有接触端子，该晶片具有分布在其上的过程表征测试点，使得至少一个工艺表征测试位置与每个IC相邻 ; 选择两个或多个IC进行同步测试; 对于这些IC中的每一个，将所选择的IC的两个或更多个接触端子和相关联的测试位置的对应的两个或更多个接触端子耦合到多路复用器的相应输入端，每个复用器具有输出端子和选择控制输入端子 所述多路复用器可操作以选择性地提供IC接触端子或测试点接触端子与多路复用器输出端子之间的电路径; 将每个多路复用器的输出端耦合到测试器通道; 操作多路复用器，使得其输出端耦合到IC接触端子; 同时测试两个或更多IC; 在完成测试同时被测试的剩余IC之前检测所选择的IC中的至少一个的故障; 在检测到故障之后，操作多路复用器，使其输出端耦合到测试点接触端; 并在完成测试剩余的IC之前收集过程表征数据。

公开(公告)号：US07638366B2

公开(公告)日：2009-12-29

申请号：US11339102

申请日：2006-01-23

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/00

CPC classification number: H01L23/5382 ,  H01L21/76838 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A conductor carrier provides, separately manufactured, conductive pathways, on a wafer level, which may be coupled to a wafer of fully fabricated integrated circuits. Such conductor carriers include an insulating body having two major surfaces with conductors disposed on each of those surfaces, and conductors disposed within the insulating body so as to provide signal continuity between various conductors on each of the two surfaces. An assembly can be formed by permanently or removably attaching the conductor carrier to the wafer. Conductor carriers may include an evacuation pathway suitable for removing air, or other gases, from between the conductor and the wafer so as to create a pressure differential that urges the conductor carrier into contact with the wafer. Conductor carriers may include a groove which is suitable for receiving a sealing ring; and may include a street map which is suitable for providing guidance to a wafer sawing operation.

Abstract translation: 导体载体在晶片级上提供单独制造的导电通路，其可以耦合到完全制造的集成电路的晶片。 这种导体载体包括绝缘体，其具有两个主表面，其中布置在每个表面上的导体，以及设置在绝缘体内的导体，以便在两个表面中的每个表面上的各个导体之间提供信号连续性。 可以通过将导体载体永久地或可移除地附接到晶片来形成组件。 导体载体可以包括适于从导体和晶片之间去除空气或其它气体的抽空路径，以产生促使导体载体与晶片接触的压力差。 导体载体可以包括适于接收密封环的凹槽; 并且可以包括适于提供对晶片锯切操作的引导的街道地图。

公开(公告)号：US20090289645A1

公开(公告)日：2009-11-26

申请号：US12275226

申请日：2008-11-21

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

Abstract translation: 通过使晶片和边缘延伸的晶片转换器进入附接状态来提供对晶片的集成电路的访问以同时执行两种或更多种类型的测试。 边缘延伸晶片转换器具有设置在其上的晶片侧接触端子和询问侧接触端子，第一组晶片侧接触端子电耦合到第一组查询侧接触端子，以及第二组晶片 侧接触端子电耦合到第二组询问侧接触端子。 边缘延伸晶片转换器具有与附接的晶片大致共同延伸的中心部分，以及延伸超出通常由晶片的外圆周边缘限定的边界的边缘延伸部分。 至少一个集成电路的第一组焊盘电耦合到第一组晶片侧接触端子，并且集成电路的第二组焊盘电耦合到第二组晶片侧接触端子。 边缘延伸晶片转换器可以被成形为使得其边缘延伸部分不与其中心部分共面。

公开(公告)号：US20090224410A1

公开(公告)日：2009-09-10

申请号：US12074904

申请日：2008-03-07

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/544 ,  G01R1/07307 ,  G01R3/00 ,  H01L23/147 ,  H01L23/49827 ,  H01L2223/54453 ,  H01L2224/05001 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/00014

Abstract: Apparatus and methods are provided for wafer translators having a silicon core with copper and subjacent resin layers disposed thereon. A silicon substrate is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical drilling of via openings in a dielectric material; plating of copper, nickel, and gold layers; laser removal of metal; and chemical removal of metal; in order to produce a wafer translator having a silicon core. In further aspects of the present invention, alignment marks are formed and contact structures, such as stud bumps, are placed relative to a local set of alignment marks.

Abstract translation: 提供了一种用于晶片转换器的装置和方法，其具有设置在其上的铜和相邻树脂层的硅芯。 对硅基板进行许多印刷电路板制造操作，包括但不限于施加树脂被覆铜箔; 铜层机械研磨; 电介质材料中通孔的机械钻孔; 电镀铜，镍和金层; 激光去除金属; 和化学除去金属; 以产生具有硅芯的晶片转换器。 在本发明的另外的方面，形成对准标记，并且相对于本地对准标记集合放置诸如柱形凸起的接触结构。

公开(公告)号：US07579852B2

公开(公告)日：2009-08-25

申请号：US12079202

申请日：2008-03-24

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  H01R9/00

CPC classification number: G01R1/0491

Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

Abstract translation: 用于晶片转换器的金属化图案提供适合于元件放置的交错接触焊盘的高密度布局，以及适于连接到外部设备端子的较大接触焊盘。 在另一方面，可以将导电材料添加到交叉指接触垫和较大接触垫的高密度布局或从其移除，以修改或重新配置晶片转换器的电路径。

公开(公告)号：US07532021B2

公开(公告)日：2009-05-12

申请号：US11810951

申请日：2007-06-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R31/286

Abstract: A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract translation: 一种翻译的晶片待机测试仪（TWST），它是能够模拟被测翻译的晶片的形状因子和一些或所有行为的混合设备，其可操作以直接或远程存储，量化，编码和传送， 来自测试系统的数据，包括但不限于焊盘压力，电接触和温度。 TWST可以包括几个堆叠和连接的层，至少一个内层，包括可操作以与测试系统相互作用的电子组件。

公开(公告)号：US07453277B2

公开(公告)日：2008-11-18

申请号：US11810950

申请日：2007-06-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R31/2863 ,  G01R31/2875

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.

Abstract translation: 组件包括衬底，例如印刷电路板，其上布置有第一阵列的接触焊盘; 引导环结构，其设置在所述基板上并且至少部分地围绕所述第一接触焊盘阵列; 设置在所述第一接触焊盘阵列上的转换器插座，所述转换器插座适于接收翻译的晶片的测试器侧; 适于设置在晶片的背面上方的导热的，共形的散热垫; 适于装配在所述第一接触焊盘阵列上的盖板，与所述引导环结构对准，在其中包含设置在所述第一接触焊盘阵列上的各种部件，并且可移除地附接到所述衬底; 以及适于可拆卸地附接到基底的第二侧的枕板。 在另一方面，翻译的晶片设置在翻译器插座上方，使得翻译器的测试器侧与翻译器插座接触; 并且散热垫设置在翻译的晶片的背面上。 在另一方面，衬底包括信号通信装置，例如但不限于适于耦合到通常设置在印刷电路板上的各种控制器电路的边缘连接器。

公开(公告)号：US07379641B1

公开(公告)日：2008-05-27

申请号：US11799550

申请日：2007-05-01

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G02B6/26 ,  G02B6/04 ,  G02B6/42 ,  G02B6/30

CPC classification number: G02B6/4222 ,  G01R31/2891 ,  G02B6/04 ,  G02B6/4226 ,  G02B6/4227

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

公开(公告)号：US07020957B2

公开(公告)日：2006-04-04

申请号：US10789287

申请日：2004-02-27

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01R9/00

CPC classification number: H01R12/523 ,  H01R12/7082 ,  H01R13/514 ,  H01R13/6592 ,  H01R13/6599 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: Coax and twinax connector assemblies, suitable for low-cost manufacturing and high-frequency performance, include one or more slices of insulating material having a series of through-holes therein. Dimensions of the through-holes are tailored to the dimensions of the coax or twinax that are to be fitted to such connector assemblies. The slices may have dimensions that are uniform to within typical manufacturing tolerances. By combining, or stacking, the slices, the connector height can be customized to a particular application. A variety of slice thicknesses are provided so that a variety of final connector heights may be achieved. Conductive material sheets may be disposed between one or more pairs of connector slices so as to provide a common ground connection for one or more conductors, such as, for example, ground shields, disposed in the through-holes of the stacked connector slices. Additionally, right angle connectors and low-cost twinax cables are disclosed.

Abstract translation: 适用于低成本制造和高频性能的同轴电缆和双轴连接器组件包括在其中具有一系列通孔的一个或多个绝缘材料片。 通孔的尺寸适合于将要安装到这种连接器组件的同轴或双轴的尺寸。 切片可以具有在典型制造公差内均匀的尺寸。 通过组合或堆叠切片，连接器高度可以根据特定应用进行定制。 提供了各种切片厚度，使得可以实现各种最终的连接器高度。 导电材料片可以设置在一对或多对连接器片之间，以便为布置在堆叠的连接器片的通孔中的一个或多个导体（例如接地屏蔽）提供公共接地连接。 此外，公开了直角连接器和低成本双轴电缆。

公开(公告)号：USRE46075E1

公开(公告)日：2016-07-19

申请号：US13475811

申请日：2012-05-18

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/2863 ,  G01R31/2875

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.

Abstract translation: 组件包括衬底，例如印刷电路板，其上布置有第一阵列的接触焊盘; 引导环结构，其设置在所述基板上并且至少部分地围绕所述第一接触焊盘阵列; 设置在所述第一接触焊盘阵列上的转换器插座，所述转换器插座适于接收翻译的晶片的测试器侧; 适于设置在晶片的背面上方的导热的，共形的散热垫; 适于装配在所述第一接触焊盘阵列上的盖板，与所述引导环结构对准，在其中包含设置在所述第一接触焊盘阵列上的各种部件，并且可移除地附接到所述衬底; 以及适于可拆卸地附接到基底的第二侧的枕板。 在另一方面，翻译的晶片设置在翻译器插座上方，使得翻译器的测试器侧与翻译器插座接触; 并且散热垫设置在翻译的晶片的背面上。 在另一方面，衬底包括信号通信装置，例如但不限于适于耦合到通常设置在印刷电路板上的各种控制器电路的边缘连接器。