A method for fabricating a device, the method including: providing a first layer including first transistors wherein the first transistors include mono-crystalline semiconductor and first alignment marks; overlaying a second semiconductor layer over the first layer, wherein the second layer includes second transistors, the second transistors include mono-crystalline semiconductor and are configured to be memory cells, at least one of the memory cells include a floating body region configured to be charged to a level indicative of a state of the memory cell, and fabricating the second transistors includes alignment to the first alignment marks.