公开(公告)号：US09099526B2

公开(公告)日：2015-08-04

申请号：US13251269

申请日：2011-10-02

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/02 ,  H01L21/762 ,  H01L21/683 ,  H01L21/822 ,  H01L21/84 ,  H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L23/36 ,  H01L23/00

CPC classification number: H01L21/76232 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/16 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/80047 ,  H01L2224/802 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

Abstract: A device, including: an integrated circuit chip, where the integrated circuit chip includes: a first layer including a plurality of first transistors including a mono-crystal channel; at least one metal layer overlying the first layer, the at least one metal layer including aluminum or copper and providing interconnection between the first transistors; a second layer overlying the at least one metal layer, the second layer including second horizontally oriented transistors including a second mono-crystal channel; and a through the second layer via of diameter less than 150 nm, where the second horizontally oriented transistors are interconnected to form logic circuits.

Abstract translation: 一种器件，包括：集成电路芯片，其中所述集成电路芯片包括：包括多个第一晶体管的第一层，所述第一晶体管包括单晶通道; 覆盖在第一层上的至少一个金属层，所述至少一个金属层包括铝或铜并提供第一晶体管之间的互连; 覆盖所述至少一个金属层的第二层，所述第二层包括包括第二单晶通道的第二水平取向晶体管; 以及通过直径小于150nm的第二层通孔，其中第二水平取向晶体管互连以形成逻辑电路。

公开(公告)号：US08664042B2

公开(公告)日：2014-03-04

申请号：US13471009

申请日：2012-05-14

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/00

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Abstract translation: 一种构建可配置系统的方法，所述方法包括：提供包括第一管芯和第二管芯的第一可配置系统，其中第一管芯和第二管芯之间的连接包括穿硅通孔（“TSV”），其中 使用第一骰子线从第一晶片切下第一芯片; 提供包括第三管芯和第四管芯的第二可配置系统，其中第三管芯和第四管芯之间的连接包括穿硅通孔（“TSV”），其中使用第三管芯从第三晶片切割第三管芯 线条 以及使用相同的至少20个掩模来处理所述第一晶片和所述第三晶片; 其中第一骰子线与第三骰子线基本上不同，并且其中第二骰子包括用于将第一可配置系统连接到外部装置的可配置I / O。

公开(公告)号：US20140059411A1

公开(公告)日：2014-02-27

申请号：US13593895

申请日：2012-08-24

Applicant: Zvi Or-Bach ,  Ze'ev Wurman ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Ze'ev Wurman ,  Brian Cronquist

IPC: G06F17/21

CPC classification number: G06F17/211 ,  G06F16/5846 ,  G06F17/2235 ,  G06F17/2765

Abstract: A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier.

Abstract translation: 一种包括处理器，显示器，指示装置和存储器的计算系统; 其中所述存储器包括文本文件，对应于所述文本文件的图形文件和至少执行这些动作的可执行指令（i）识别显示的文本文件内的字母数字标识符的选择，然后（ii）识别 相应图形文件中的标识符，然后（iii）显示包括标识符的外观的图形文件的页面。

公开(公告)号：US08476145B2

公开(公告)日：2013-07-02

申请号：US12904119

申请日：2010-10-13

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L21/30

CPC classification number: H01L21/6835 ,  H01L21/823431 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method to fabricate a semiconductor device, including the sequence of: implanting one or more regions on a semiconductor wafer forming a doped layer; performing a first transfer of the doped layer onto a carrier; and then performing a second transfer of the doped layer from the carrier to a target wafer; and then etching said one or more regions of the doped layer to form transistors on the doped layer.

Abstract translation: 一种制造半导体器件的方法，包括以下顺序：在形成掺杂层的半导体晶片上注入一个或多个区域; 执行掺杂层到载体上的第一次转移; 然后执行掺杂层从载体到目标晶片的第二次转移; 然后蚀刻掺杂层的一个或多个区域以在掺杂层上形成晶体管。

公开(公告)号：US20130083589A1

公开(公告)日：2013-04-04

申请号：US13624968

申请日：2012-09-23

Applicant: Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Paul Lim

IPC: G11C11/34 ,  G11C11/40 ,  G11C11/00 ,  G11C11/24

CPC classification number: H01L27/10873 ,  G11C5/025 ,  G11C5/063 ,  G11C11/406 ,  G11C2211/4016 ,  H01L24/16 ,  H01L24/94 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 以及包括第二晶体管并覆盖所述至少一个金属层的第二单结晶半导体层，其中所述至少一个金属层位于所述第一半导体层和所述第二单结晶半导体层之间，其中所述第二单结晶半导体层 半导体层的厚度小于100nm，其中第二晶体管包括水平取向的晶体管。

公开(公告)号：US08395191B2

公开(公告)日：2013-03-12

申请号：US12900379

申请日：2010-10-07

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L29/76 ,  H01L29/772 ,  H01L25/065

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.

Abstract translation: 一种半导体器件，包括具有第一晶体管的第一单晶层和第一对准标记; 覆盖所述第一单晶层的至少一个金属层，其中所述至少一个金属层包括铜或铝; 以及包括激活的掺杂剂区域的第二层，所述第二层覆盖所述至少一个金属层，其中所述第二层包括第二晶体管，其中所述第二晶体管被处理成与所述第一对准标记对齐，具有小于100nm的对准误差， 第二晶体管包括单晶，水平取向晶体管。

公开(公告)号：US07960242B2

公开(公告)日：2011-06-14

申请号：US12847911

申请日：2010-07-30

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC classification number: G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用基于所述第一对准标记和所述第二对准标记之间的未对准的对准来执行光刻。

公开(公告)号：US20110108888A1

公开(公告)日：2011-05-12

申请号：US12949617

申请日：2010-11-18

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC: H01L27/118

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract translation: 半导体器件包括包括第一晶体管的第一单结晶层和形成第一晶体管之间的连接的至少一部分的第一金属层; 以及包括第二晶体管的第二层，所述第二晶体管包括单晶材料，所述第二层覆盖所述第一金属层，其中所述第一金属层包括铝或铜，并且其中所述第二层的厚度小于1微米，并且包括 逻辑单元。

公开(公告)号：US20210242189A1

公开(公告)日：2021-08-05

申请号：US17151867

申请日：2021-01-19

Applicant: Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/473 ,  H01L21/768 ,  H01L25/00

Abstract: A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.

公开(公告)号：US08907442B2

公开(公告)日：2014-12-09

申请号：US13492382

申请日：2012-06-08

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/50 ,  H01L21/98 ,  H01L21/822 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L23/48

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device, including: a first layer including first transistors; an interconnection layer overlying the first transistors, the interconnection layer providing interconnection for the first transistors; a bonding layer overlying the interconnection layer; a second layer overlying the bonding layer; and a carrier substrate for the transferring of the second layer, where the second layer includes at least one through second layer via, where the at least one through second layer via has a diameter of less than 100 nm, where the second layer includes a plurality of second transistors, and where the second layer is transferred from a donor wafer.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管的互连层，所述互连层为所述第一晶体管提供互连; 覆盖所述互连层的接合层; 覆盖结合层的第二层; 以及用于转移第二层的载体衬底，其中第二层包括至少一个贯穿第二层通孔，其中至少一个贯穿第二层通孔具有小于100nm的直径，其中第二层包括多个 的第二晶体管，并且其中第二层从施主晶片转移。