Invention Grant
US08481377B2 Method for manufacturing a semiconductor device with impurity doped oxide semiconductor
有权
制造具有杂质掺杂氧化物半导体的半导体器件的方法
- Patent Title: Method for manufacturing a semiconductor device with impurity doped oxide semiconductor
- Patent Title (中): 制造具有杂质掺杂氧化物半导体的半导体器件的方法
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Application No.: US13026518Application Date: 2011-02-14
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Publication No.: US08481377B2Publication Date: 2013-07-09
- Inventor: Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
- Applicant: Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2010-035423 20100219
- Main IPC: H01L21/338
- IPC: H01L21/338

Abstract:
It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
Public/Granted literature
- US20110204362A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2011-08-25
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