Invention Grant
US08486843B2 Method of forming nanoscale three-dimensional patterns in a porous material
有权
在多孔材料中形成纳米级三维图案的方法
- Patent Title: Method of forming nanoscale three-dimensional patterns in a porous material
- Patent Title (中): 在多孔材料中形成纳米级三维图案的方法
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Application No.: US13062130Application Date: 2009-09-01
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Publication No.: US08486843B2Publication Date: 2013-07-16
- Inventor: Xiuling Li , David N. Ruzic , Ik Su Chun , Edmond K. C. Chow , Randolph E. Flauta
- Applicant: Xiuling Li , David N. Ruzic , Ik Su Chun , Edmond K. C. Chow , Randolph E. Flauta
- Applicant Address: US IL Urbana
- Assignee: The Board of Trustrees of the University of Illinois
- Current Assignee: The Board of Trustrees of the University of Illinois
- Current Assignee Address: US IL Urbana
- Agency: Brinks Hofer Gilson & Lione
- International Application: PCT/US2009/055590 WO 20090901
- International Announcement: WO2010/027962 WO 20100311
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/3213

Abstract:
A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.
Public/Granted literature
- US20110263119A1 METHOD OF FORMING NANOSCALE THREE-DIMENSIONAL PATTERNS IN A POROUS MATERIAL Public/Granted day:2011-10-27
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