中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.011 seconds)

    Method of forming an array of high aspect ratio semiconductor nanostructures
    2.
    发明授权
    Method of forming an array of high aspect ratio semiconductor nanostructures 有权
    形成高纵横比半导体纳米结构阵列的方法

    公开(公告)号：US08980656B2

    公开(公告)日：2015-03-17

    申请号：US13503123

    申请日：2010-10-14

    Applicant: Xiuling Li ,  Nicholas X. Fang ,  Placid M. Ferreira ,  Winston Chern ,  Ik Su Chun ,  Keng Hao Hsu

    Inventor： Xiuling Li ,  Nicholas X. Fang ,  Placid M. Ferreira ,  Winston Chern ,  Ik Su Chun ,  Keng Hao Hsu

    IPC: H01L21/00 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06

    CPC classification number: H01L21/3081 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L29/0676 ,  Y10S977/893

    Abstract: A new method for forming an array of high aspect ratio semiconductor nanostructures entails positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate. The surface of the stamp includes a pattern of relief features in contact with the conductive film so as to define a film-stamp interface. A flux of metal ions is generated across the film-stamp interface, and a pattern of recessed features complementary to the pattern of relief features is created in the conductive film. The recessed features extend through an entire thickness of the conductive film to expose the underlying semiconductor substrate and define a conductive pattern on the substrate. The stamp is removed, and material immediately below the conductive pattern is selectively removed from the substrate. Features are formed in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1.

    Abstract translation: 用于形成高纵横比半导体纳米结构阵列的新方法需要将包含固体电解质的印模的表面定位成与设置在半导体衬底上的导电膜相对。 印模的表面包括与导电膜接触的凹凸图案，以便限定胶片印记界面。 在膜 - 印迹界面上产生金属离子通量，并且在导电膜中产生与凹凸特征图案互补的凹陷特征图案。 凹陷特征延伸穿过导电膜的整个厚度以暴露下面的半导体衬底并且在衬底上限定导电图案。 去除印模，并且从基板选择性地去除导电图案之下的材料。 在半导体衬底中形成具有至少约5:1的长宽比纵横比的特征。

    Metal-assisted chemical etch porous silicon formation method
    3.
    发明授权
    Metal-assisted chemical etch porous silicon formation method 有权
    金属辅助化学蚀刻多孔硅的形成方法

    公开(公告)号：US06790785B1

    公开(公告)日：2004-09-14

    申请号：US09662682

    申请日：2000-09-15

    Applicant: Xiuling Li ,  Paul W. Bohn ,  Jonathan V. Sweedler

    Inventor： Xiuling Li ,  Paul W. Bohn ,  Jonathan V. Sweedler

    IPC: H01L21302

    CPC classification number: H01L21/0203

    Abstract: A thin discontinuous layer of metal such as Au, Pt, or Au/Pd is deposited on a silicon surface. The surface is then etched in a solution including HF and an oxidant for a brief period, as little as a couple seconds to one hour. A preferred oxidant is H2O2. Morphology and light emitting properties of porous silicon can be selectively controlled as a function of the type of metal deposited, Si doping type, silicon doping level, and/or etch time. Electrical assistance is unnecessary during the chemical etching of the invention, which may be conducted in the presence or absence of illumination.

    Abstract translation: 金属如Au，Pt或Au / Pd的薄的不连续层沉积在硅表面上。 然后将表面在包含HF和氧化剂的溶液中蚀刻短暂时间，只需几秒至1小时。 优选的氧化剂是H 2 O 2。 可以选择性地控制多孔硅的形态和发光性质，作为沉积金属，Si掺杂类型，硅掺杂水平和/或蚀刻时间的函数。 在本发明的化学蚀刻期间不需要电辅助，其可以在存在或不存在照明的情况下进行。

    Method of fabricating a planar semiconductor nanowire
    4.
    发明授权
    Method of fabricating a planar semiconductor nanowire 有权
    制造平面半导体纳米线的方法

    公开(公告)号：US08810009B2

    公开(公告)日：2014-08-19

    申请号：US12989558

    申请日：2009-04-24

    Applicant: Xiuling Li ,  Seth A. Fortuna

    Inventor： Xiuling Li ,  Seth A. Fortuna

    IPC: H01L29/04 ,  H01L21/02

    CPC classification number: H01L21/02521 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/02664 ,  Y10S977/762 ,  Y10S977/938

    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.

    Abstract translation: 组合物包括半导体衬底，其具有平行于衬底的表面定向的结晶平面和至少一个外延地设置在衬底上的平面半导体纳米线，其中纳米线沿着平行于晶体平面的衬底的结晶方向排列。 为了制造平面半导体纳米线，在半导体衬底上提供至少一个纳米颗粒，该半导体衬底具有平行于衬底的表面取向的结晶平面。 半导体衬底在处理单元中的第一温度窗内被加热。 将半导体前体添加到处理单元中，并且在第二温度窗内从衬底上的纳米颗粒生长平面半导体纳米线。 平面半导体纳米线在与晶体平面平行的衬底的晶体方向上生长。

    METHOD OF FORMING AN ARRAY OF HIGH ASPECT RATIO SEMICONDUCTOR NANOSTRUCTURES
    6.
    发明申请
    METHOD OF FORMING AN ARRAY OF HIGH ASPECT RATIO SEMICONDUCTOR NANOSTRUCTURES 有权
    形成高比例半导体纳米结构阵列的方法

    公开(公告)号：US20130052762A1

    公开(公告)日：2013-02-28

    申请号：US13503123

    申请日：2010-10-14

    Applicant: Xiuling Li ,  Nicholas X. Fang ,  Placid M. Ferreira ,  Winston Chern ,  Ik Su Chun ,  Keng Hao Hsu

    Inventor： Xiuling Li ,  Nicholas X. Fang ,  Placid M. Ferreira ,  Winston Chern ,  Ik Su Chun ,  Keng Hao Hsu

    IPC: H01L21/20 ,  H01L33/04

    CPC classification number: H01L21/3081 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L29/0676 ,  Y10S977/893

    Abstract: A new method for forming an array of high aspect ratio semiconductor nanostructures entails positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate. The surface of the stamp includes a pattern of relief features in contact with the conductive film so as to define a film-stamp interface. A flux of metal ions is generated across the film-stamp interface, and a pattern of recessed features complementary to the pattern of relief features is created in the conductive film. The recessed features extend through an entire thickness of the conductive film to expose the underlying semiconductor substrate and define a conductive pattern on the substrate. The stamp is removed, and material immediately below the conductive pattern is selectively removed from the substrate. Features are formed in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1.

    Abstract translation: 形成高纵横比半导体纳米结构阵列的新方法需要将包含固体电解质的印模的表面定位成与设置在半导体衬底上的导电膜相对。 印模的表面包括与导电膜接触的凹凸图案，以便限定胶片印记界面。 在膜 - 印迹界面上产生金属离子通量，并且在导电膜中产生与凹凸特征图案互补的凹陷特征图案。 凹陷特征延伸穿过导电膜的整个厚度以暴露下面的半导体衬底并且在衬底上限定导电图案。 去除印模，并且从基板选择性地去除导电图案之下的材料。 在半导体衬底中形成具有至少约5:1的长宽比纵横比的特征。

    METHOD OF FABRICATING A PLANAR SEMICONDUCTOR NANOWIRE
    8.
    发明申请
    METHOD OF FABRICATING A PLANAR SEMICONDUCTOR NANOWIRE 有权
    制备平面半导体纳米线的方法

    公开(公告)号：US20110121434A1

    公开(公告)日：2011-05-26

    申请号：US12989558

    申请日：2009-04-24

    Applicant: Xiuling Li ,  Seth A. Fortuna

    Inventor： Xiuling Li ,  Seth A. Fortuna

    IPC: H01L29/04 ,  H01L21/338 ,  H01L21/36 ,  B82Y99/00 ,  B82Y40/00

    CPC classification number: H01L21/02521 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/02664 ,  Y10S977/762 ,  Y10S977/938

    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.

    Abstract translation: 组合物包括半导体衬底，其具有平行于衬底的表面定向的结晶平面和至少一个外延地设置在衬底上的平面半导体纳米线，其中纳米线沿着平行于晶体平面的衬底的结晶方向排列。 为了制造平面半导体纳米线，在半导体衬底上提供至少一个纳米颗粒，该半导体衬底具有平行于衬底的表面取向的结晶平面。 半导体衬底在处理单元中的第一温度窗内被加热。 将半导体前体添加到处理单元中，并且在第二温度窗内从衬底上的纳米颗粒生长平面半导体纳米线。 平面半导体纳米线在与晶体平面平行的衬底的晶体方向上生长。

    Metal-assisted chemical etch to produce porous group III-V materials
    9.
    发明授权
    Metal-assisted chemical etch to produce porous group III-V materials 有权
    金属辅助化学蚀刻产生多孔III-V族材料

    公开(公告)号：US06762134B2

    公开(公告)日：2004-07-13

    申请号：US09989050

    申请日：2001-11-20

    Applicant: Paul W. Bohn ,  Xiuling Li ,  Jonathan V. Sweedler ,  Ilesanmi Adesida

    Inventor： Paul W. Bohn ,  Xiuling Li ,  Jonathan V. Sweedler ,  Ilesanmi Adesida

    IPC: H01L21302

    CPC classification number: H01L21/30612 ,  H01L21/0332 ,  H01L21/3081 ,  H01L33/18 ,  H01L33/30

    Abstract: A thin discontinuous layer of metal such as Au, Pt, or Au/Pd is deposited on a Group III-V material surface. The surface is then etched in a solution including HF and an oxidant for a preferably brief period, as little as a couple seconds to one hour. A preferred oxidant is H2O2. Morphology and light emitting properties of porous Group III-V material can be selectively controlled as a function of the type of metal deposited, doping type, doping level, metal thickness, whether emission is collected on or off the metal coated areas and/or etch time. Electrical assistance is unnecessary during the chemical etching of the invention, which may be conducted in the presence or absence of illumination.

    Abstract translation: 在III-V族材料表面上沉积诸如Au，Pt或Au / Pd之类的金属薄的不连续层。 然后将表面蚀刻在包含HF和氧化剂的溶液中，优选短暂的时间，几小时至几小时。 优选的氧化剂是H 2 O 2。 可以选择性地控制多孔III-V族材料的形态和发光性质，作为金属沉积类型，掺杂类型，掺杂水平，金属厚度，是否在金属涂层区域或/或金属涂层区域上收集发射的函数的函数 时间。 在本发明的化学蚀刻期间不需要电辅助，其可以在存在或不存在照明的情况下进行。

Patent Agency Ranking