Invention Grant
US08487348B2 Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
有权
减少非平面晶体管结构中基于布局的应变变化的方法和装置
- Patent Title: Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
- Patent Title (中): 减少非平面晶体管结构中基于布局的应变变化的方法和装置
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Application No.: US13588416Application Date: 2012-08-17
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Publication No.: US08487348B2Publication Date: 2013-07-16
- Inventor: Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
- Applicant: Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
Public/Granted literature
- US20120305990A1 METHODS AND APPARATUS TO REDUCE LAYOUT BASED STRAIN VARIATIONS IN NON-PLANAR TRANSISTOR STRUCTURES Public/Granted day:2012-12-06
Information query
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