Invention Grant
- Patent Title: Clock delay circuit and delay locked loop including the same
- Patent Title (中): 时钟延迟电路和延迟锁定环包括相同
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Application No.: US13232555Application Date: 2011-09-14
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Publication No.: US08493116B2Publication Date: 2013-07-23
- Inventor: Jong-Ryun Choi , Seong-Ook Jung , Suho Kim , Heechai Kang , Kyungho Ryu
- Applicant: Jong-Ryun Choi , Seong-Ook Jung , Suho Kim , Heechai Kang , Kyungho Ryu
- Applicant Address: KR KR Seoul
- Assignee: Samsung Electronics Co., Ltd.,Industry-Academic Cooperation Foundation, Yonsei University
- Current Assignee: Samsung Electronics Co., Ltd.,Industry-Academic Cooperation Foundation, Yonsei University
- Current Assignee Address: KR KR Seoul
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2010-0090336 20100915
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.
Public/Granted literature
- US20120062294A1 CLOCK DELAY CIRCUIT AND DELAY LOCKED LOOP INCLUDING THE SAME Public/Granted day:2012-03-15
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