CLOCK DELAY CIRCUIT AND DELAY LOCKED LOOP INCLUDING THE SAME
    1.
    发明申请
    CLOCK DELAY CIRCUIT AND DELAY LOCKED LOOP INCLUDING THE SAME 有权
    时钟延迟电路和延迟锁定环路,包括它

    公开(公告)号:US20120062294A1

    公开(公告)日:2012-03-15

    申请号:US13232555

    申请日:2011-09-14

    CPC classification number: H03H11/26 H03L7/0814

    Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.

    Abstract translation: 数字延迟线在其中包括多个延迟单元。 延迟线被配置为响应于编码所选择的数量的不连续的温度计代码,通过使周期信号通过选定数量的多个延迟单元来延迟在其第一输入处接收到的周期信号。 提供了一种代码转换器,其包括组位解码器,共享位解码器和代码输出单元阵列,它们被共同配置为响应二进制控制代码产生不连续的温度计代码。

    Clock delay circuit and delay locked loop including the same
    2.
    发明授权
    Clock delay circuit and delay locked loop including the same 有权
    时钟延迟电路和延迟锁定环包括相同

    公开(公告)号:US08493116B2

    公开(公告)日:2013-07-23

    申请号:US13232555

    申请日:2011-09-14

    CPC classification number: H03H11/26 H03L7/0814

    Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.

    Abstract translation: 数字延迟线在其中包括多个延迟单元。 延迟线被配置为响应于编码所选择的数量的不连续的温度计代码,通过使周期信号通过选定数量的多个延迟单元来延迟在其第一输入处接收到的周期信号。 提供了一种代码转换器,其包括组位解码器,共享位解码器和代码输出单元阵列,它们被共同配置为响应二进制控制代码产生不连续的温度计代码。

    Digital DLL including skewed gate type duty correction circuit and duty correction method thereof
    3.
    发明授权
    Digital DLL including skewed gate type duty correction circuit and duty correction method thereof 有权
    数字DLL包括偏斜门型占空比校正电路及其占空比校正方法

    公开(公告)号:US08519758B2

    公开(公告)日:2013-08-27

    申请号:US13046073

    申请日:2011-03-11

    CPC classification number: H03K5/1565 G11C7/222 H03L7/0814

    Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

    Abstract translation: 提供了可以包括在数据处理装置中的延迟锁定环(DLL),并且可以包括这样的DLL的占空比校正电路和占空比校正方法。 占空比校正方法包括:在时钟的第一次转换时对输出时钟进行二次转换,对输出时钟的第一次转换进行占空比校正的时钟采样,以检测占空比的误差,并执行占空比 根据检测到的占空比误差,使用偏斜栅极链进行校正。

    DIGITAL DLL INCLUDING SKEWED GATE TYPE DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF
    4.
    发明申请
    DIGITAL DLL INCLUDING SKEWED GATE TYPE DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF 有权
    数字DLL,其中包括门锁类型校正电路及其校正方法

    公开(公告)号:US20110221495A1

    公开(公告)日:2011-09-15

    申请号:US13046073

    申请日:2011-03-11

    CPC classification number: H03K5/1565 G11C7/222 H03L7/0814

    Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

    Abstract translation: 提供了可以包括在数据处理装置中的延迟锁定环(DLL),并且可以包括这样的DLL的占空比校正电路和占空比校正方法。 占空比校正方法包括:在时钟的第一次转换时对输出时钟进行二次转换,对输出时钟的第一次转换进行占空比校正的时钟采样,以检测占空比的误差,并执行占空比 根据检测到的占空比误差,使用偏斜栅极链进行校正。

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