发明授权
US08501602B2 Method of manufacturing devices having vertical junction edge 有权
制造具有垂直接合边缘的器件的方法

Method of manufacturing devices having vertical junction edge
摘要:
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
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