Invention Grant
US08504751B2 Integrated circuit package with multiple dies and interrupt processing
有权
具有多个模具和中断处理的集成电路封装
- Patent Title: Integrated circuit package with multiple dies and interrupt processing
- Patent Title (中): 具有多个模具和中断处理的集成电路封装
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Application No.: US12960713Application Date: 2010-12-06
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Publication No.: US08504751B2Publication Date: 2013-08-06
- Inventor: Andrew Michael Jones , Stuart Ryan
- Applicant: Andrew Michael Jones , Stuart Ryan
- Applicant Address: GB Marlow, Buckinghamshire
- Assignee: STMicroelectronics (R&D) Ltd.
- Current Assignee: STMicroelectronics (R&D) Ltd.
- Current Assignee Address: GB Marlow, Buckinghamshire
- Agency: Gardere Wynne Sewell LLP
- Priority: EP09178184 20091207
- Main IPC: G06F13/24
- IPC: G06F13/24

Abstract:
A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.
Public/Granted literature
- US20110138093A1 INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND INTERRUPT PROCESSING Public/Granted day:2011-06-09
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