公开(公告)号：US08571016B2

公开(公告)日：2013-10-29

申请号：US13161361

申请日：2011-06-15

Applicant: Ignazio Urzi ,  Daniele Mangano ,  Claire Bonnet

Inventor： Ignazio Urzi ,  Daniele Mangano ,  Claire Bonnet

IPC: H04L12/66

CPC classification number: G06F15/7825

Abstract: A plurality of inputs are configured to receive circuit switched traffic from a plurality of initiators. A plurality of outputs are configured to output said traffic to a network on chip. Each output is associated with a different quality of service traffic. A traffic controller directs the received circuit switched traffic to respective ones of the outputs in dependence on a quality of service associated with the traffic.

Abstract translation: 多个输入被配置为从多个发起者接收电路交换业务。 多个输出被配置为将所述业务输出到芯片上的网络。 每个输出与不同的服务质量流量相关联。 交通控制器根据与业务相关联的服务质量将接收到的电路交换业务指向相应的输出。

公开(公告)号：US08477222B2

公开(公告)日：2013-07-02

申请号：US11559113

申请日：2006-11-13

Applicant: Justin Richardson

Inventor： Justin Richardson

IPC: H04N5/235

CPC classification number: H04N5/35554 ,  G06K7/10722 ,  G06K7/10752 ,  H04N5/3532

Abstract: In a solid state image sensor having a pixel array, a first frame is imaged using varying exposure times in a series of zones. The exposure time for a subsequent frame is selected from the results of the first frame, The exposure times are controlled in a rolling blade manner by controlling the number of lines between reset and readout. The sensor is particularly suited to use in bar code readers.

Abstract translation: 在具有像素阵列的固态图像传感器中，在一系列区域中使用变化的曝光时间对第一帧进行成像。 从第一帧的结果中选择后续帧的曝光时间。通过控制复位和读出之间的行数，以滚动刀片的方式控制曝光时间。 传感器特别适用于条码阅读器。

公开(公告)号：US20130155282A1

公开(公告)日：2013-06-20

申请号：US13710198

申请日：2012-12-10

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Robert Golding

IPC: H01L27/146 ,  H04N5/335

CPC classification number: H01L27/14609 ,  G01N21/645 ,  H04N5/335 ,  H04N5/35572 ,  H04N5/378

Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.

Abstract translation: 一种像素读出电路，至少包括第一，第二和第三存储单元。 在像素的积分期间，像素读出电路在积分期间反复取样像素输出电平，将第一样本存储在第一存储器位置，并将每个后续样本存储在第一存储单元以外的存储位置。 存储每个样品的时间对应于该采样时间，使得在存储了前三个样品之后的任何一个时间，至少存储了第一样品和两个最近的样品。 还公开了一种在未定义的积分周期内读出像素输出的相应方法。

公开(公告)号：US20130151792A1

公开(公告)日：2013-06-13

申请号：US13705435

申请日：2012-12-05

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： David Smith

IPC: G06F3/06

CPC classification number: G06F13/102 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0614 ,  G06F5/06 ,  G06F13/16 ,  G06F13/423 ,  G06F15/167

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Abstract translation: 一种处理器模块，包括配置成与至少一个另外的处理器模块处理器共享数据的处理器; 以及存储器映射外设，被配置为与至少一个另外的处理器存储器映射的外围设备通信以控制所述数据的共享，其中所述存储器映射的外围设备包括发送器部分，所述发送器部分包括数据请求生成器， 取决于来自处理器的数据请求寄存器写入信号的模块; 以及确认等待信号发生器，其被配置为根据来自所述另外的处理器模块的数据确认信号将确认等待信号输出到所述处理器，其中所述数据请求生成器数据请求指示符还依赖于所述数据确认信号和所述确认等待信号发生器 确认等待信号还取决于确认等待寄存器写入信号。

公开(公告)号：US08446482B2

公开(公告)日：2013-05-21

申请号：US12112146

申请日：2008-04-30

Applicant: Craig McNaughton

Inventor： Craig McNaughton

IPC: H04N5/235

CPC classification number: H04N21/4344 ,  H04N7/56 ,  H04N19/00 ,  H04N21/2343 ,  H04N21/2353 ,  H04N21/236 ,  H04N21/23608 ,  H04N21/23611 ,  H04N21/4348

Abstract: An image processing device including an encoder processor and a decoder circuit. The encoder processor receives image data from a sensor and encodes the data with padding data if a series of bytes indicative of command sequence occur within the image data. The decoder circuit receives the image data and the padding data, and removes the padding data from within the image data.

Abstract translation: 一种包括编码器处理器和解码器电路的图像处理装置。 编码器处理器从传感器接收图像数据，并且如果在图像数据内发生表示命令序列的一系列字节，则用填充数据对数据进行编码。 解码器电路接收图像数据和填充数据，并从图像数据内移除填补数据。

公开(公告)号：US20130031312A1

公开(公告)日：2013-01-31

申请号：US13560491

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract translation: 一种高速缓冲存储器控制器，包括：预取请求器，被配置为发出预取请求，每个预取请求具有多个不同服务质量中的一个。

公开(公告)号：US07831945B2

公开(公告)日：2010-11-09

申请号：US11372235

申请日：2006-03-09

Applicant: Paul Barnes

Inventor： Paul Barnes

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.

Abstract translation: 一种在集成电路中设计时钟分配网络的方法，所述方法包括：创建具有最大驱动强度的所有小区的时钟分配网络; 将时钟分配网络的参数提供给定时分析工具; 在时序分析工具中，在迭代过程中分析时钟分配网络的时序，包括操纵时钟分配网络中的至少一个小区的驱动强度，并评估是否有改进的时序，其中迭代过程停止在哪里 时机没有改善; 并输出驱动强度变化的单元的列表。

公开(公告)号：US09842067B2

公开(公告)日：2017-12-12

申请号：US14951023

申请日：2015-11-24

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED

Inventor： David Smith

IPC: G06F3/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F15/167 ,  G06F1/10 ,  G06F5/06 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0614 ,  G06F5/06 ,  G06F13/16 ,  G06F13/423 ,  G06F15/167

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

公开(公告)号：US20140028556A1

公开(公告)日：2014-01-30

申请号：US14001731

申请日：2012-02-03

Applicant: Jeffrey Raynor ,  Pascal Mellot

Inventor： Jeffrey Raynor ,  Pascal Mellot

IPC: G06F3/033

CPC classification number: G06F3/033 ,  G06F3/0304 ,  G06F3/03547 ,  G06F3/038 ,  G06F2203/04101

Abstract: An optical navigation device is provided for detecting movement of a pointer, such as a finger, in three dimensions. A sensor obtains images of the pointer which have been illuminated by an illumination source, and an image scaling module determines the difference in size between images acquired by the image sensor to determine the difference in height of the pointer between images.

Abstract translation: 提供了一种光学导航装置，用于检测诸如手指的指示器在三维中的移动。 传感器获得由照明源照亮的指示器的图像，并且图像缩放模块确定由图像传感器获取的图像之间的尺寸差异，以确定图像之间的指针高度差。

公开(公告)号：US08537263B2

公开(公告)日：2013-09-17

申请号：US12969956

申请日：2010-12-16

Applicant: Mathieu Reigneau

Inventor： Mathieu Reigneau

IPC: H04N5/225 ,  G06F3/033

CPC classification number: G06F3/042 ,  G01R21/00 ,  G06F3/0421 ,  G06G7/24

Abstract: The imaging device has an imaging surface and a sensor, wherein the imaging surface is illuminated and reflects at least some of the illumination to the sensor to detect an image. The imaging device has a width and an optical path passing therethrough, wherein the optical path exhibits distortion as a result of the width of the device and the nature of the optical path. The imaging device includes an optical element which in use compensates for the distortion by generating a magnification profile across a tangential plane of the device at the sensor.

Abstract translation: 成像装置具有成像表面和传感器，其中成像表面被照亮并且将至少一些照明反射到传感器以检测图像。 成像装置具有穿过其中的宽度和光路，其中光路由于装置的宽度和光路的性质而呈现变形。 该成像装置包括光学元件，该光学元件在使用中通过在该传感器处跨越该装置的切向平面生成放大轮廓来补偿该失真。