Invention Grant
US08518792B2 Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure
有权
用于制造具有与三维晶体管结构对准的铁电电容器的镶嵌自对准铁电随机存取存储器（F-RAM）的方法
- Patent Title: Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure
- Patent Title (中): 用于制造具有与三维晶体管结构对准的铁电电容器的镶嵌自对准铁电随机存取存储器（F-RAM）的方法
-
Application No.: US13569785Application Date: 2012-08-08
-
Publication No.: US08518792B2Publication Date: 2013-08-27
- Inventor: Shan Sun , Thomas E. Davenport , John Cronin
- Applicant: Shan Sun , Thomas E. Davenport , John Cronin
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/20
- IPC: H01L21/20
Abstract:
Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
Public/Granted literature
Information query
IPC分类:
