A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.