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公开(公告)号：US20120302057A1
公开(公告)日：2012-11-29
申请号：US13558441
申请日：2012-07-26
IPC分类号： H01L21/768
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 然后，形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 然后将第一沟槽延伸穿过硬掩模，并且暴露的区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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公开(公告)号：US08518824B2
公开(公告)日：2013-08-27
申请号：US13558441
申请日：2012-07-26
IPC分类号： H01L21/311 , H01L21/44 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 然后，形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 然后将第一沟槽延伸穿过硬掩模，并且暴露的区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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公开(公告)号：US08298943B1
公开(公告)日：2012-10-30
申请号：US13118034
申请日：2011-05-27
IPC分类号： H01L21/311 , H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. The first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 第一沟槽延伸穿过硬掩模，并且暴露区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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公开(公告)号：US20140023834A1
公开(公告)日：2014-01-23
申请号：US13571496
申请日：2012-08-10
IPC分类号： B32B3/10
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144 , Y10T428/24802
摘要： At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
摘要翻译： 在衬底上形成的至少一个掩模层包括电介质材料和金属材料中的至少一种。 通过在所述至少一个掩模层之一中形成第一图案，形成包括所述第一图案的图案化掩模层。 在所述图案化掩模层上形成包括包括至少一个阻挡区域的第二图案的覆盖结构。 除去不在所述阻挡区域下面的所述图案化掩模层的部分被去除。 图案化掩模层的其余部分包括作为第一图案和第二图案的交叉的复合图案。 图案化掩模层包括电介质材料或金属材料，因此能够将高保真图案转移到下面的材料层中。
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5.发明申请FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION 失效包括金属硬质合金层的薄膜堆叠，用于边缘图像传输金场效应晶体管形成公开(公告)号：US20130001749A1
公开(公告)日：2013-01-03
申请号：US13171865
申请日：2011-06-29
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/845
摘要： A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
摘要翻译： 一种用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模和大特征（FX）掩模，所述膜堆叠包括位于绝缘体上的硅（SOI）层 在金属硬掩模层下面; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 并使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模蚀刻到SOI层中。
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公开(公告)号：US20140024219A1
公开(公告)日：2014-01-23
申请号：US13552992
申请日：2012-07-19
IPC分类号： H01L21/306
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144 , Y10T428/24802
摘要： At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
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公开(公告)号：US08637406B1
公开(公告)日：2014-01-28
申请号：US13552992
申请日：2012-07-19
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144 , Y10T428/24802
摘要： At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
摘要翻译： 在衬底上形成的至少一个掩模层包括电介质材料和金属材料中的至少一种。 通过在所述至少一个掩模层之一中形成第一图案，形成包括所述第一图案的图案化掩模层。 在所述图案化掩模层上形成包括包括至少一个阻挡区域的第二图案的覆盖结构。 除去不在所述阻挡区域下面的所述图案化掩模层的部分被去除。 图案化掩模层的其余部分包括作为第一图案和第二图案的交叉的复合图案。 图案化掩模层包括电介质材料或金属材料，因此能够将高保真图案转移到下面的材料层中。
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8.发明申请FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION 有权包括金属硬质合金层的薄膜堆叠，用于边缘图像传输金场效应晶体管形成公开(公告)号：US20130001750A1
公开(公告)日：2013-01-03
申请号：US13171868
申请日：2011-06-29
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/3088 , H01L21/3086 , H01L21/845 , H01L29/66795
摘要： A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
摘要翻译： 用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模，所述膜堆叠包括位于金属硬掩模层下面的绝缘体上硅层（SOI）层; 在金属硬掩模层上形成大特征（FX）掩模; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模刻蚀成SOI层。
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9.发明授权Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation 有权薄膜堆叠包括用于侧壁图像转移翅片场效应晶体管形成的金属硬掩模层公开(公告)号：US08586482B2
公开(公告)日：2013-11-19
申请号：US13171868
申请日：2011-06-29
IPC分类号： H01L21/311
CPC分类号： H01L21/3088 , H01L21/3086 , H01L21/845 , H01L29/66795
摘要： A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
摘要翻译： 用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模，所述膜堆叠包括位于金属硬掩模层下面的绝缘体上硅层（SOI）层; 在金属硬掩模层上形成大特征（FX）掩模; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模刻蚀成SOI层。
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10.发明授权Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation 失效薄膜堆叠包括用于侧壁图像转移翅片场效应晶体管形成的金属硬掩模层公开(公告)号：US08580692B2
公开(公告)日：2013-11-12
申请号：US13171865
申请日：2011-06-29
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/845
摘要： A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
摘要翻译： 一种用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模和大特征（FX）掩模，所述膜堆叠包括位于绝缘体上的硅（SOI）层 金属硬掩模层下面; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 并使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模蚀刻到SOI层中。
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