Invention Grant
- Patent Title: Normally-off power JFET and manufacturing method thereof
- Patent Title (中): 常关断电源JFET及其制造方法
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Application No.: US13363256Application Date: 2012-01-31
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Publication No.: US08524552B2Publication Date: 2013-09-03
- Inventor: Koichi Arai , Yasuaki Kagotoshi , Nobuo Machida , Natsuki Yokoyama , Haruka Shimizu
- Applicant: Koichi Arai , Yasuaki Kagotoshi , Nobuo Machida , Natsuki Yokoyama , Haruka Shimizu
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2011-019438 20110201
- Main IPC: H01L21/337
- IPC: H01L21/337

Abstract:
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
Public/Granted literature
- US20120193641A1 NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF Public/Granted day:2012-08-02
Information query
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