公开(公告)号：US08569132B2

公开(公告)日：2013-10-29

申请号：US13361010

申请日：2012-01-30

申请人： Nobuo Machida ,  Koichi Arai

发明人： Nobuo Machida ,  Koichi Arai

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068

摘要： In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.

摘要翻译： 在基于SiC的MISFET及其制造方法中，在引入杂质之后，需要极高温的活化退火。 因此，难以频繁地使用在硅系MISFET制造工序中进行的自对准工序。 这导致了为了控制装置的特性，高精度对准技术是必不可少的问题。 根据本发明，在诸如使用碳化硅基半导体衬底的基于SiC的垂直功率MISFET等半导体器件及其制造方法中，形成沟道区，源极区和栅极结构 相互自我约束的关系

公开(公告)号：US08378413B2

公开(公告)日：2013-02-19

申请号：US13032080

申请日：2011-02-22

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US08377775B2

公开(公告)日：2013-02-19

申请号：US13396816

申请日：2012-02-15

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20120289013A1

公开(公告)日：2012-11-15

申请号：US13559113

申请日：2012-07-26

申请人： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

发明人： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC分类号： H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

摘要翻译： 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20080233696A1

公开(公告)日：2008-09-25

申请号：US12071542

申请日：2008-02-22

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US07361557B2

公开(公告)日：2008-04-22

申请号：US11653404

申请日：2007-01-16

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US07358141B2

公开(公告)日：2008-04-15

申请号：US11483547

申请日：2006-07-11

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

公开(公告)号：US07172941B2

公开(公告)日：2007-02-06

申请号：US10984788

申请日：2004-11-10

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20050082609A1

公开(公告)日：2005-04-21

申请号：US10984788

申请日：2004-11-10

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/12 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US4357512A

公开(公告)日：1982-11-02

申请号：US171542

申请日：1980-07-23

申请人： Koji Nishimoto ,  Kenji Higuchi ,  Toshiyuki Oki ,  Nobuo Machida

发明人： Koji Nishimoto ,  Kenji Higuchi ,  Toshiyuki Oki ,  Nobuo Machida

IPC分类号： B23K11/087 ,  B23K13/02 ,  H05B6/06 ,  H05B6/40

CPC分类号： B23K13/02 ,  B23K11/0873

摘要： An apparatus for continuous manufacture of butt-welded pipes is constituted by a heating furnace for heating a skelp continuously passed therethrough up to a predetermined temperature less than the butt-welding temperature for the material of the skelp, heaters adjacent the outlet end of the heating furnace and having spaced opposed induction heating coils on opposite sides of the path along which the skelp is passed through the heaters and adjacent the edge portions of the skelp for heating only the edge portions of the skelp discharged from the heating furnace up to the butt-welding temperature. The induction heating coils are such that the electromagnetic coupling between the induction heating coils and the corresponding edge portions of the skelp can be varied to adjust the temperature to which the edge portions are heated. A bending device adjacent the outlet end of the heaters bends the skelp into a generally tubular form, and butt-welding rolls adjacent the outlet end of the bending apparatus apply a predetermined pressure to the bent up skelp for butt-welding the edges of the skelp to each other. A cooling device along the path of the pipe between pairs of contracting rolls cools the seamed portion of the pipe to the temperature of the remainder of the pipe.

摘要翻译： 用于连续制造对接焊管的装置由加热炉构成，该加热炉用于加热连续通过的钢板，直到预定温度小于用于该钢板的材料的对接焊接温度，加热器邻近加热出口端 炉子，并且在路径的相对侧上具有间隔开的相对的感应加热线圈，沿着该相对侧的边缘通过加热器并且邻近边缘部分，仅加热从加热炉排出的边缘部分的边缘部分， 焊接温度。 感应加热线圈使得感应加热线圈和边缘部分的相应边缘部分之间的电磁耦合可以改变以调节边缘部分被加热到的温度。 邻近加热器的出口端的弯曲装置将骨架弯曲成大致管状的形式，邻近弯曲装置的出口端的对接辊对弯曲的边缘施加预定的压力，用于对接边缘的边缘 对彼此。 沿着成对的收缩辊之间的管道的冷却装置将管的接合部分冷却到管的其余部分的温度。