Invention Grant
US08524562B2 Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
有权
用于在非硅沟道MOS器件中降低费米能级引脚的方法
- Patent Title: Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
- Patent Title (中): 用于在非硅沟道MOS器件中降低费米能级引脚的方法
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Application No.: US12560282Application Date: 2009-09-15
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Publication No.: US08524562B2Publication Date: 2013-09-03
- Inventor: Wei-E Wang , Han Chung Lin , Marc Meuris
- Applicant: Wei-E Wang , Han Chung Lin , Marc Meuris
- Applicant Address: BE Leuven
- Assignee: IMEC
- Current Assignee: IMEC
- Current Assignee Address: BE Leuven
- Agency: Knobbe, Martens Olson & Bear, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
Public/Granted literature
- US20100065824A1 METHOD FOR REDUCING FERMI-LEVEL-PINNING IN A NON-SILICON CHANNEL MOS DEVICE Public/Granted day:2010-03-18
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