公开(公告)号：US20120098063A1

公开(公告)日：2012-04-26

申请号：US12910000

申请日：2010-10-22

Applicant: Yung-Chih Tsai ,  Han-Chung Lin

Inventor： Yung-Chih Tsai ,  Han-Chung Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823835 ,  H01L21/326 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/402 ,  H01L29/404 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括在衬底中形成的第一掺杂区和第二掺杂区。 第一和第二掺杂区域是相对掺杂的。 半导体器件包括形成在衬底上的第一栅极。 第一栅极覆盖第一掺杂区域的一部分和第二掺杂区域的一部分。 半导体器件包括在衬底上形成的第二栅极。 第二栅极覆盖第二掺杂区域的不同部分。 半导体器件包括向第二栅极提供第一电压的第一电压源。 半导体器件包括向第二掺杂区域提供第二电压的第二电压源。 第一和第二电压彼此不同。

公开(公告)号：US07633130B2

公开(公告)日：2009-12-15

申请号：US11725350

申请日：2007-03-19

Applicant: Tobin J. Marks ,  Peide Ye ,  Antonio Facchetti ,  Gang Lu ,  Han Chung Lin

Inventor： Tobin J. Marks ,  Peide Ye ,  Antonio Facchetti ,  Gang Lu ,  Han Chung Lin

IPC: H01L29/76

CPC classification number: H01L51/052 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02299 ,  H01L21/3122

Abstract: Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.

Abstract translation: 包括III-V半导体和有机栅极介电材料的场效应晶体管器件，诸如能够在器件设计和制造中提供灵活性的介电材料。

公开(公告)号：US08552495B2

公开(公告)日：2013-10-08

申请号：US12910000

申请日：2010-10-22

Applicant: Yung-Chih Tsai ,  Han-Chung Lin

Inventor： Yung-Chih Tsai ,  Han-Chung Lin

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L21/823835 ,  H01L21/326 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/402 ,  H01L29/404 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

公开(公告)号：US08524562B2

公开(公告)日：2013-09-03

申请号：US12560282

申请日：2009-09-15

Applicant: Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

Inventor： Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

IPC: H01L21/336

CPC classification number: H01L21/3003 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3006 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/78

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract translation: 在金属氧化物半导体（MOS）器件中的诸如Ge和III-V化合物（例如GaAs或InGaAs）的高迁移率半导体化合物通道中减少（避免）费米能级固定（FLP）的方法。 该方法使用原子氢，其使高迁移率半导体化合物的界面与栅极电介质钝化，并进一步修复缺陷。 该方法进一步改善了MOS器件特性，使得产生具有量子阱的MOS器件。

公开(公告)号：US20100065824A1

公开(公告)日：2010-03-18

申请号：US12560282

申请日：2009-09-15

Applicant: Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

Inventor： Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L21/3003 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3006 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/78

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract translation: 在金属氧化物半导体（MOS）器件中的诸如Ge和III-V化合物（例如GaAs或InGaAs）的高迁移率半导体化合物通道中减少（避免）费米能级固定（FLP）的方法。 该方法使用原子氢，其使高迁移率半导体化合物的界面与栅极电介质钝化，并进一步修复缺陷。 该方法进一步改善了MOS器件特性，使得产生具有量子阱的MOS器件。