公开(公告)号：US08288291B2

公开(公告)日：2012-10-16

申请号：US12021006

申请日：2008-01-28

Applicant: Sonja Sioncke ,  Marc Meuris

Inventor： Sonja Sioncke ,  Marc Meuris

IPC: H01L21/302

CPC classification number: C23F1/18 ,  C23F3/06 ,  H01L21/02052

Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 μm×2 μm) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.

Abstract translation: 本发明提供了用于从III-V半导体衬底去除体金属污染的单步方法。 该方法包括将金属污染的III-V半导体衬底浸入硫酸与过氧化物的混合物中，硫酸与过氧化物（例如过氧化氢）的体积比在约3:1至约9:1之间。 在用硫酸过氧化物混合物处理III-V半导体衬底之后，可以从衬底基本上除去体金属污染物，而处理后的衬底的表面粗糙度低于约0.5nm RMS（2μm×2μm）是 获得。 本发明还提供一种在形成半导体器件的处理步骤之前，通过根据本发明的单步方法去除大块金属污染来制造半导体器件的方法。

公开(公告)号：US20080214013A1

公开(公告)日：2008-09-04

申请号：US12021006

申请日：2008-01-28

Applicant: Sonja Sioncke ,  Marc Meuris

Inventor： Sonja Sioncke ,  Marc Meuris

IPC: H01L21/306

CPC classification number: C23F1/18 ,  C23F3/06 ,  H01L21/02052

Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 μm×2 μm) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.

Abstract translation: 本发明提供了用于从III-V半导体衬底去除体金属污染的单步方法。 该方法包括将金属污染的III-V半导体衬底浸入硫酸与过氧化物的混合物中，硫酸与过氧化物（例如过氧化氢）的体积比在约3:1至约9:1之间。 在用硫酸过氧化物混合物处理III-V半导体衬底之后，可以从衬底基本上除去体金属污染物，同时获得处理后的衬底的表面粗糙度低于约0.5nm RMS（2m 2 x 2 mum）。 本发明还提供一种在形成半导体器件的处理步骤之前，通过根据本发明的单步方法去除大块金属污染来制造半导体器件的方法。

公开(公告)号：US06799588B1

公开(公告)日：2004-10-05

申请号：US10031923

申请日：2002-04-17

Applicant: Ulrich Speh ,  Jens Schneider ,  Marc Meuris

Inventor： Ulrich Speh ,  Jens Schneider ,  Marc Meuris

IPC: B08B304

CPC classification number: H01L21/67057 ,  H01L21/67051 ,  Y10S134/902

Abstract: The aim of the invention is to attain a uniform and homogeneous treatment of substrates in a device comprising at least one process container which is arranged in a gas atmosphere and which contains a treatment fluid. Said process container also comprises at least two openings which are located underneath a treatment fluid surface and through which the substrates are linearly guided. In addition, an overflow for the treatment fluid is provided.

Abstract translation: 本发明的目的是在包括至少一个处理容器的装置中实现均匀且均匀的处理基板，所述处理容器布置在气体气氛中并且包含处理流体。 所述处理容器还包括位于处理流体表面下方的至少两个开口，并且基底线被直线地引导。 此外，提供了处理流体的溢流。

公开(公告)号：US20110140087A1

公开(公告)日：2011-06-16

申请号：US13034592

申请日：2011-02-24

Applicant: Geert Hellings ,  Geert Eneman ,  Marc Meuris

Inventor： Geert Hellings ,  Geert Eneman ,  Marc Meuris

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7783 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract translation: 公开了一种量子阱器件及其制造方法。 一方面，该器件包括覆盖衬底的量子阱区域，覆盖量子阱区域的一部分的栅极区域，与栅极区域相邻的源极和漏极区域。 量子阱区域包括覆盖在衬底上并包括具有第一带隙的半导体材料的缓冲结构，覆盖缓冲结构的沟道结构，包括具有第二带隙的半导体材料，以及覆盖沟道结构的阻挡层， 具有第三带隙的掺杂半导体材料。 第一和第三带隙比第二带隙宽。 源区和漏区中的每一个与栅极区自对准，并且包括具有比第二带隙宽的掺杂区和第四带隙的半导体材料。

公开(公告)号：US20080169485A1

公开(公告)日：2008-07-17

申请号：US11963615

申请日：2007-12-21

Applicant: Marc Heyns ,  Marc Meuris

Inventor： Marc Heyns ,  Marc Meuris

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/778 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.

Abstract translation: 公开了一种半导体器件。 在一个方面，该器件包括沟道区，沟道区包括沟道层，其中当晶体管导通时，其中电荷载流子可以移动，以使电流通过晶体管。 该装置还包括与沟道层接触的源极区域和漏极区域，以向沟道层提供电流和从沟道层提供电流。 该方法还包括栅极，优选地在栅电极和沟道层之间设置有栅极电介质。 沟道层可以包括III-V材料，并且源极和漏极区域包括SiGe，SixGe1-x，x在0和100％之间，排列成使得III-V材料和SiGe之间存在异质结，其中异质结 被定向成与栅极电介质或栅电极相交。

公开(公告)号：US20060086950A1

公开(公告)日：2006-04-27

申请号：US11249642

申请日：2005-10-13

Applicant: Matty Caymax ,  Renaud Bonzom ,  Frederik Leys ,  Marc Meuris

Inventor： Matty Caymax ,  Renaud Bonzom ,  Frederik Leys ,  Marc Meuris

IPC: H01L29/732

CPC classification number: H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/31608 ,  H01L21/31645

Abstract: The present invention is related to a method for making a passivated semiconductor substrate comprising the steps of providing a substrate surface comprising or consisting of mono-crystalline semiconductor material other than silicon and forming a silicon layer on the substrate surface, such that the silicon layer is substantially lattice matched to the mono-crystalline semiconductor material. It is also related to a semiconductor substrate passivated according to the method.

Abstract translation: 本发明涉及一种用于制造钝化半导体衬底的方法，包括以下步骤：提供包含硅以外的单晶半导体材料或由其构成的衬底表面，并在衬底表面上形成硅层，使得硅层为 基本上与单晶半导体材料晶格匹配。 它还与根据该方法钝化的半导体衬底有关。

公开(公告)号：US08354344B2

公开(公告)日：2013-01-15

申请号：US12201948

申请日：2008-08-29

Applicant: David Brunco ,  Marc Meuris

Inventor： David Brunco ,  Marc Meuris

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract translation: 本发明涉及半导体处理领域，更具体地说，涉及在锗基片上形成低电阻层。 本发明的一个方面是一种方法，包括：提供其上暴露锗层的至少一个区域的基底; 在衬底和所述锗区域上沉积金属，例如Co或Ni; 在所述金属上形成由氧化硅含有层，氮化硅层或钨层构成的覆盖层，优选为SiO 2层; 然后退火金属锗化物形成; 然后选择性地去除所述覆盖层和任何未反应的金属，其中用于形成所述覆盖层形成的温度低于退火温度。

公开(公告)号：US20090283756A1

公开(公告)日：2009-11-19

申请号：US12463338

申请日：2009-05-08

Applicant: Geert Hellings ,  Geert Eneman ,  Marc Meuris

Inventor： Geert Hellings ,  Geert Eneman ,  Marc Meuris

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7783 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract translation: 公开了一种量子阱器件及其制造方法。 一方面，该器件包括覆盖衬底的量子阱区域，覆盖量子阱区域的一部分的栅极区域，与栅极区域相邻的源极和漏极区域。 量子阱区域包括覆盖在衬底上并包括具有第一带隙的半导体材料的缓冲结构，覆盖缓冲结构的沟道结构，包括具有第二带隙的半导体材料，以及覆盖沟道结构的阻挡层， 具有第三带隙的掺杂半导体材料。 第一和第三带隙比第二带隙宽。 源区和漏区中的每一个与栅极区自对准，并且包括具有比第二带隙宽的掺杂区和第四带隙的半导体材料。

公开(公告)号：US06632751B2

公开(公告)日：2003-10-14

申请号：US09892269

申请日：2001-06-27

Applicant: Paul Mertens ,  Marc Meuris

Inventor： Paul Mertens ,  Marc Meuris

IPC: H01L2100

CPC classification number: H01L21/67057 ,  B08B3/04 ,  F26B13/10 ,  F26B13/28 ,  H01L21/67028 ,  Y10S134/902

Abstract: The present invention is related to a method and apparatus for liquid treating and drying a substrate, such as a semiconductor wafer, the method comprising the step of immersing a substrate or a batch of substrates in a tank filled with a liquid, and removing the substrate(s) through an opening so that a flow of the liquid takes place through the opening during removal of the substrate. Simultaneously with the removal, a reduction of the surface tension of the liquid is caused to take place near the intersection line between the liquid and the substrate. For acquiring such a tensio-active effect, a uniform flow of a gas or vapor is used, or/and a local application of heat. The invention is equally related to an apparatus for performing the method of the invention.

Abstract translation: 本发明涉及一种用于液体处理和干燥诸如半导体晶片的衬底的方法和装置，该方法包括以下步骤：将衬底或一批衬底浸入填充有液体的槽中，并除去衬底 通过开口，使得在去除基底期间通过开口发生液体流。 与去除同时，在液体和基板之间的交线处附近发生液体的表面张力的降低。 为了获得这种张力积极效应，使用气体或蒸汽的均匀流动，或/和局部施加热量。 本发明同样涉及用于执行本发明方法的装置

公开(公告)号：US06530385B2

公开(公告)日：2003-03-11

申请号：US09751569

申请日：2000-12-29

Applicant: Marc Meuris ,  Paul Mertens ,  Marc Heyns

Inventor： Marc Meuris ,  Paul Mertens ,  Marc Heyns

IPC: B08B304

CPC classification number: H01L21/67057 ,  H01L21/67086 ,  Y10S134/902

Abstract: An apparatus for wet cleaning or etching of flat substrates comprising a tank with an inlet opening and outlet opening for said substrates. Said tank contains a cleaning liquid and is installed in a gaseous environment. At least one of the openings is a slice in a sidewall of the tank and is present below the liquid-surface. In the tank there may be a portion above the liquid filled with a gas with a pressure being lower than the pressure within said environment. The method comprises the step of transferring a substrate through the cleaning or etching liquid at a level underneath the surface of said liquid making use of said apparatus.