Invention Grant
US08536041B2 Method for fabricating transistor with high-K dielectric sidewall spacer
有权
用于制造具有高K电介质侧壁间隔物的晶体管的方法
- Patent Title: Method for fabricating transistor with high-K dielectric sidewall spacer
- Patent Title (中): 用于制造具有高K电介质侧壁间隔物的晶体管的方法
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Application No.: US13559182Application Date: 2012-07-26
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Publication No.: US08536041B2Publication Date: 2013-09-17
- Inventor: Leland Chang , Isaac Lauer , Jeffrey W. Sleight
- Applicant: Leland Chang , Isaac Lauer , Jeffrey W. Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini & Bianco PL
- Agent Stephen Bongini
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/01

Abstract:
A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
Public/Granted literature
- US20120289014A1 METHOD FOR FABRICATING TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER Public/Granted day:2012-11-15
Information query
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