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    8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES
    1.
    发明申请
    8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES 有权
    具有肖特基二极管的8晶体管SRAM单元设计

    公开(公告)号：US20130176769A1

    公开(公告)日：2013-07-11

    申请号：US13345619

    申请日：2012-01-06

    申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC分类号： G11C11/40

    CPC分类号： G11C11/417 ,  G11C11/412

    摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.

    摘要翻译： 一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

    Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance
    2.
    发明授权
    Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance 有权
    制造具有第一和第二硅侧壁以降低寄生电容的金属高K晶体管的工艺

    公开(公告)号：US08216907B2

    公开(公告)日：2012-07-10

    申请号：US12880478

    申请日：2010-09-13

    申请人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    发明人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/8238 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

    CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

    摘要翻译： 一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层; 选择性地仅去除第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

    Metal high dielectric constant transistor with reverse-T gate
    3.
    发明授权
    Metal high dielectric constant transistor with reverse-T gate 失效
    具有反T型栅极的金属高介电常数晶体管

    公开(公告)号：US07736981B2

    公开(公告)日：2010-06-15

    申请号：US12113527

    申请日：2008-05-01

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L29/72

    CPC分类号： H01L29/4908 ,  H01L21/28114 ,  H01L29/42384 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

    摘要： A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.

    摘要翻译： 提供晶体管。 晶体管包括包含源极区和漏极区的硅层。 栅极堆叠设置在源极区域和漏极区域之间的硅层上。 栅堆叠包括高介电常数材料的第一层，包含金属或金属合金的第二层，以及包含硅或多晶硅的第三层。 栅极堆叠的第二层的横向范围基本上大于栅极堆叠的第三层的横向范围。 还提供了制造这种晶体管的方法。

    SELF-ALIGNED SOI SCHOTTKY BODY TIE EMPLOYING SIDEWALL SILICIDATION
    4.
    发明申请
    SELF-ALIGNED SOI SCHOTTKY BODY TIE EMPLOYING SIDEWALL SILICIDATION 审中-公开
    自对准SOI肖特基身体采用侧壁硅酸盐

    公开(公告)号：US20100032759A1

    公开(公告)日：2010-02-11

    申请号：US12189639

    申请日：2008-08-11

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/78612 ,  H01L29/66772

    摘要： A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel.

    摘要翻译： 自对准硅绝缘体（SOI）肖特基体系结构包括：源极区，包括设置在源极区的顶表面上的硅化物层; 漏极区，包括设置在所述漏极区的顶表面上的硅化物层; 栅极区域，设置在由漏极和源极区域形成的沟道上方; 以及栅极氧化物层，其设置在由漏极和源极区域形成的栅极区域和沟道之间，其中当对扩散区域进行硅化时，其形成金属 - 硅合金接触，使得硅化物层延伸到沟道中并直接接触沟道 。

    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same
    5.
    发明申请
    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same 有权
    具有硅侧壁的金属高K晶体管用于减少寄生电容，以及制造相同的工艺

    公开(公告)号：US20100006956A1

    公开(公告)日：2010-01-14

    申请号：US12539842

    申请日：2009-08-12

    申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78

    CPC分类号： H01L29/517 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

    摘要翻译： 公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。 该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。 该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。 耗尽的侧壁层是非晶硅或多晶硅之一。 该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

    Method for fabricating transistor with high-K dielectric sidewall spacer
    6.
    发明授权
    Method for fabricating transistor with high-K dielectric sidewall spacer 有权
    用于制造具有高K电介质侧壁间隔物的晶体管的方法

    公开(公告)号：US08536041B2

    公开(公告)日：2013-09-17

    申请号：US13559182

    申请日：2012-07-26

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L27/01

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

    摘要翻译： 提供了一种用于制造晶体管的方法。 该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。 栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。 还提供了制造这种晶体管的方法。

    8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
    7.
    发明申请
    8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
    具有外部门极二极管的8晶体管SRAM单元设计

    公开(公告)号：US20130176771A1

    公开(公告)日：2013-07-11

    申请号：US13345636

    申请日：2012-01-06

    申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC分类号： G11C11/40

    CPC分类号： G11C16/24 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

    摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

    摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极 线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same
    8.
    发明申请
    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same 有权
    具有硅侧壁的金属高K晶体管，用于减少寄生电容，以及制造相同的工艺

    公开(公告)号：US20120187506A1

    公开(公告)日：2012-07-26

    申请号：US13432395

    申请日：2012-03-28

    申请人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    发明人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

    摘要翻译： 一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层，选择性地去除 仅第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same
    10.
    发明申请
    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same 有权
    具有硅侧壁的金属高K晶体管用于减少寄生电容，以及制造相同的工艺

    公开(公告)号：US20100327376A1

    公开(公告)日：2010-12-30

    申请号：US12880478

    申请日：2010-09-13

    申请人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    发明人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

    摘要翻译： 一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层; 选择性地仅去除第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。