Invention Grant
US08543860B2 Multi-core clocking system with interlocked ‘anti-freeze’ mechanism
有权
具有互锁“防冻”机制的多核心计时系统
- Patent Title: Multi-core clocking system with interlocked ‘anti-freeze’ mechanism
- Patent Title (中): 具有互锁“防冻”机制的多核心计时系统
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Application No.: US13059246Application Date: 2008-08-26
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Publication No.: US08543860B2Publication Date: 2013-09-24
- Inventor: Derek Beattie , Carl Culshaw , Alan Devine , James Andrew Collier Scobie
- Applicant: Derek Beattie , Carl Culshaw , Alan Devine , James Andrew Collier Scobie
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/IB2008/053414 WO 20080826
- International Announcement: WO2010/023501 WO 20100304
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F1/00 ; G06F15/00 ; G06F11/00

Abstract:
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.
Public/Granted literature
- US20110145625A1 MULTI-CORE CLOCKING SYSTEM WITH INTERLOCKED 'ANTI-FREEZE' MECHANISM Public/Granted day:2011-06-16
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