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    Interrupt controller and a method of controlling processing of interrupt requests by a plurality of processing units
    4.
    发明授权
    Interrupt controller and a method of controlling processing of interrupt requests by a plurality of processing units 有权
    中断控制器以及由多个处理单元控制中断请求处理的方法

    公开(公告)号：US09575911B2

    公开(公告)日：2017-02-21

    申请号：US14246832

    申请日：2014-04-07

    Applicant: David McMenamin ,  James Andrew Collier Scobie

    Inventor： David McMenamin ,  James Andrew Collier Scobie

    IPC: G06F11/00 ,  G06F13/26 ,  G06F11/20

    CPC classification number: G06F13/26 ,  G06F11/2069 ,  G06F11/2089 ,  G06F11/2092 ,  G06F11/2094 ,  G06F2201/805

    Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.

    Abstract translation: 一种用于控制多个处理单元对中断请求的处理的中断控制器。 处理单元至少有两种模式：活动模式和非活动模式。 中断控制器包括控制器输入，耦合到控制器输入的中断路由器和监视单元。 监控单元如果确定选择的处理单元，其响应于接收到的中断请求，中断服务程序的执行被初始路由，则向中断路由器输出路由改变信号处于非活动模式，而预选的 一个处于活动模式。 中断路由器将中断服务程序的执行重新路由到预选的处理单元。

    Method, system and integrated circuit for enabling access to a memory element
    5.
    发明授权
    Method, system and integrated circuit for enabling access to a memory element 有权
    用于允许访问存储元件的方法，系统和集成电路

    公开(公告)号：US08966286B2

    公开(公告)日：2015-02-24

    申请号：US13133958

    申请日：2009-01-05

    Applicant: Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

    Inventor： Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

    IPC: G06F11/30 ,  G06F21/31 ,  G06F21/79

    CPC classification number: G06F21/31 ,  G06F21/79

    Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

    Abstract translation: 系统包括可操作地耦合到至少一个存储器元件的信号处理逻辑，并且被布置为使得能够访问所述至少一个存储器元件。 所述信号处理逻辑被配置为接收安全密钥，使用所接收的安全密钥和系统特定的种子来生成系统密钥，将生成的系统密钥与存储在所述至少一个存储器的存储区域中的参考密钥进行比较 记忆元素 信号处理逻辑还被布置为至少部分地基于所生成的系统密钥与存储在存储器中的参考密钥的比较来配置对至少一个存储器元件的访问级别。

    MULTI-CORE CLOCKING SYSTEM WITH INTERLOCKED 'ANTI-FREEZE' MECHANISM
    6.
    发明申请
    MULTI-CORE CLOCKING SYSTEM WITH INTERLOCKED 'ANTI-FREEZE' MECHANISM 有权
    具有互锁“防冻”机制的多芯钟系统

    公开(公告)号：US20110145625A1

    公开(公告)日：2011-06-16

    申请号：US13059246

    申请日：2008-08-26

    Applicant: Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

    Inventor： Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

    IPC: G06F1/04

    CPC classification number: G06F1/04

    Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

    Abstract translation: 时钟系统包括多个时钟数据处理装置和时钟控制电路，时钟控制电路控制多个时钟信号的产生以及时钟信号到多个数据处理装置的应用，允许对数据中的至少一个进行时钟 处理设备，同时冻结所有数据处理设备中的至少一个。 一种用于计时多个时钟数据处理装置的方法包括：控制多个时钟信号的产生并控制对多个数据处理装置的时钟信号的应用，允许在冻结期间对数据处理装置中的至少一个进行计时 所有这些数据处理设备中的至少一个。

    INTERRUPT CONTROLLER AND A METHOD OF CONTROLLING PROCESSING OF INTERRUPT REQUESTS BY A PLURALITY OF PROCESSING UNITS
    7.
    发明申请
    INTERRUPT CONTROLLER AND A METHOD OF CONTROLLING PROCESSING OF INTERRUPT REQUESTS BY A PLURALITY OF PROCESSING UNITS 有权
    中断控制器和一种处理单元处理中断请求的方法

    公开(公告)号：US20150286595A1

    公开(公告)日：2015-10-08

    申请号：US14246832

    申请日：2014-04-07

    Applicant: DAVID MCMENAMIN ,  JAMES ANDREW COLLIER SCOBIE

    Inventor： DAVID MCMENAMIN ,  JAMES ANDREW COLLIER SCOBIE

    IPC: G06F13/26

    CPC classification number: G06F13/26 ,  G06F11/2069 ,  G06F11/2089 ,  G06F11/2092 ,  G06F11/2094 ,  G06F2201/805

    Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.

    Abstract translation: 一种用于控制多个处理单元对中断请求的处理的中断控制器。 处理单元至少有两种模式：活动模式和非活动模式。 中断控制器包括控制器输入，耦合到控制器输入的中断路由器和监视单元。 监控单元如果确定选择的处理单元，其响应于接收到的中断请求，中断服务程序的执行被初始路由，则将其转换到中断路由器，该选择处理单元处于非活动模式，而预选 一个处于活动模式。 中断路由器将中断服务程序的执行重新路由到预选的处理单元。

    METHOD, SYSTEM AND INTEGRATED CIRCUIT FOR ENABLING ACCESS TO A MEMORY ELEMENT
    8.
    发明申请
    METHOD, SYSTEM AND INTEGRATED CIRCUIT FOR ENABLING ACCESS TO A MEMORY ELEMENT 有权
    方法，系统和集成电路，用于启用对存储元件的访问

    公开(公告)号：US20110258462A1

    公开(公告)日：2011-10-20

    申请号：US13133958

    申请日：2009-01-05

    Applicant: Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

    Inventor： Alistair Robertson ,  Derek Beattie ,  James Andrew Collier Scobie

    IPC: G06F12/14

    CPC classification number: G06F21/31 ,  G06F21/79

    Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

    Abstract translation: 系统包括可操作地耦合到至少一个存储器元件的信号处理逻辑，并且被布置为使得能够访问所述至少一个存储器元件。 所述信号处理逻辑被配置为接收安全密钥，使用所接收的安全密钥和系统特定的种子来生成系统密钥，将生成的系统密钥与存储在所述至少一个存储器的存储区域中的参考密钥进行比较 记忆元素 信号处理逻辑还被布置为至少部分地基于所生成的系统密钥与存储在存储器中的参考密钥的比较来配置对至少一个存储器元件的访问级别。

    Microcontroller unit and method therefor
    9.
    发明授权
    Microcontroller unit and method therefor 有权
    微控制器单元及其方法

    公开(公告)号：US08242815B2

    公开(公告)日：2012-08-14

    申请号：US12596253

    申请日：2007-04-26

    Applicant: James Andrew Collier Scobie ,  Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Feddeler

    Inventor： James Andrew Collier Scobie ,  Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Feddeler

    IPC: H03L7/00

    CPC classification number: G06F1/30 ,  G06F1/24 ,  G06F11/0796

    Abstract: A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.

    Abstract translation: 微控制器单元包括可操作地耦合到微控制器单元的多个逻辑元件的复位控制器。 低电压检测逻辑可操作地耦合到复位控制器并被布置成经由复位控制器向微控制器单元的多个相应逻辑元件提供多个低电压中断信号。 还描述了操作微控制器单元的方法。

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