Invention Grant
US08563370B2 Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls
有权
用于制造具有空气侧壁的环形栅极硅纳米线晶体管的方法
- Patent Title: Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls
- Patent Title (中): 用于制造具有空气侧壁的环形栅极硅纳米线晶体管的方法
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Application No.: US13384215Application Date: 2011-07-04
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Publication No.: US08563370B2Publication Date: 2013-10-22
- Inventor: Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
- Applicant: Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
- Applicant Address: CN Beijing
- Assignee: Peking University
- Current Assignee: Peking University
- Current Assignee Address: CN Beijing
- Agency: Foley & Lardner LLP
- Agent Antoinette F. Konski
- Priority: CN201110139058 20110526
- International Application: PCT/CN2011/076805 WO 20110704
- International Announcement: WO2012/159314 WO 20121129
- Main IPC: H01L21/338
- IPC: H01L21/338
Abstract:
A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
Public/Granted literature
- US20120302014A1 METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR WITH AIR SIDEWALLS Public/Granted day:2012-11-29
Information query
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