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    FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR
    5.
    发明申请
    FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR 有权
    垂直硅纳米管场效应晶体管的制造方法

    公开(公告)号：US20130011980A1

    公开(公告)日：2013-01-10

    申请号：US13501711

    申请日：2011-11-18

    Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    IPC: H01L21/336 ,  B82Y40/00

    CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

    Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

    Abstract translation: 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

    Heat Dissipation Structure of SOI Field Effect Transistor
    6.
    发明申请
    Heat Dissipation Structure of SOI Field Effect Transistor 有权
    SOI场效应晶体管的散热结构

    公开(公告)号：US20130001655A1

    公开(公告)日：2013-01-03

    申请号：US13582624

    申请日：2011-08-17

    Applicant: Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

    Inventor： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

    IPC: H01L23/38 ,  H01L29/80

    CPC classification number: H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

    Abstract translation: 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

    Resource configuration method, device, and system
    7.
    发明授权
    Resource configuration method, device, and system 有权
    资源配置方法，设备和系统

    公开(公告)号：US08335477B2

    公开(公告)日：2012-12-18

    申请号：US13097849

    申请日：2011-04-29

    Applicant: Shukun Wang ,  Dingzhang Dai ,  Xin Huang ,  Boya Lv

    Inventor： Shukun Wang ,  Dingzhang Dai ,  Xin Huang ,  Boya Lv

    IPC: H04B7/005 ,  H04B7/00

    CPC classification number: H04W72/0406 ,  H04L25/00 ,  H04W52/367

    Abstract: A resource configuration method includes acquiring capability information of a base station (BS), in which the capability information of the BS includes information indicating whether the BS has channel power boost capability. Capability information of a user equipment (UE) is acquired. The capability information of the UE includes information indicating whether the UE has the channel power boost capability. The BS is notified to configure resources for performing channel estimation by using the channel power boost capability for the UE if the UE and the BS both have the channel power boost capability.

    Abstract translation: 资源配置方法包括获取基站（BS）的能力信息，其中BS的能力信息包括指示BS是否具有信道功率提升能力的信息。 获取用户设备（UE）的能力信息。 UE的能力信息包括指示UE是否具有信道功率提升能力的信息。 如果UE和BS都具有信道功率提升能力，则通知BS通过使用UE的信道功率提升能力来配置用于执行信道估计的资源。

    PRINTED CIRCUIT BOARD
    8.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20120175156A1

    公开(公告)日：2012-07-12

    申请号：US13088297

    申请日：2011-04-15

    Applicant: CHANG-XIN HUANG

    Inventor： CHANG-XIN HUANG

    IPC: H05K1/09 ,  H05K1/02

    CPC classification number: H05K3/22 ,  H05K1/0292 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/0989 ,  H05K2203/173

    Abstract: A printed circuit board includes a substrate, a plurality of metal wires, and a solder mask layer. The substrate includes a first area and a second area. The second area surrounds and does not overlap the first area. The metal wires are disposed on the first area of the substrate. One end of one of two adjacent metal wires faces one end of the other one of the two adjacent metal wires. The solder mask layer is formed on the second area of the substrate. In the present invention, a short circuit or an open circuit between the two adjacent metal wires is directly formed during processes of manufacturing the printed circuit board, whereby a jumper is not required so as to reduce a layout area, and cost of a manual post-welding treatment can be reduced.

    Abstract translation: 印刷电路板包括基板，多个金属线和焊接掩模层。 基板包括第一区域和第二区域。 第二区域围绕并且不与第一区域重叠。 金属线设置在基板的第一区域上。 两个相邻的金属线中的一个的一端面对两个相邻金属线中另一个的一端。 焊料掩模层形成在衬底的第二区域上。 在本发明中，在制造印刷电路板的过程中直接形成两个相邻的金属线之间的短路或开路，由此不需要跳线以减少布局面积和手动柱的成本 可以减少焊接处理。

    Resource Configuration Method, Device, and System
    9.
    发明申请
    Resource Configuration Method, Device, and System 有权
    资源配置方法，设备和系统

    公开(公告)号：US20110207498A1

    公开(公告)日：2011-08-25

    申请号：US13097849

    申请日：2011-04-29

    Applicant: Shukun Wang ,  Dingzhang Dai ,  Xin Huang ,  Boya Lv

    Inventor： Shukun Wang ,  Dingzhang Dai ,  Xin Huang ,  Boya Lv

    IPC: H04W52/04

    CPC classification number: H04W72/0406 ,  H04L25/00 ,  H04W52/367

    Abstract: A resource configuration method includes acquiring capability information of a base station (BS), in which the capability information of the BS includes information indicating whether the BS has channel power boost capability. Capability information of a user equipment (UE) is acquired. The capability information of the UE includes information indicating whether the UE has the channel power boost capability. The BS is notified to configure resources for performing channel estimation by using the channel power boost capability for the UE if the UE and the BS both have the channel power boost capability.

    Abstract translation: 资源配置方法包括获取基站（BS）的能力信息，其中BS的能力信息包括指示BS是否具有信道功率提升能力的信息。 获取用户设备（UE）的能力信息。 UE的能力信息包括指示UE是否具有信道功率提升能力的信息。 如果UE和BS都具有信道功率提升能力，则通知BS通过使用UE的信道功率提升能力来配置用于执行信道估计的资源。

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