Invention Grant
- Patent Title: Inactivity triggered self clocking logic family
- Patent Title (中): 不活动触发自我计时逻辑家族
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Application No.: US13426776Application Date: 2012-03-22
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Publication No.: US08575964B2Publication Date: 2013-11-05
- Inventor: Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
- Applicant: Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent David A. Cain, Esq.
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
Public/Granted literature
- US20130249596A1 INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY Public/Granted day:2013-09-26
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