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    Inactivity triggered self clocking logic family
    1.
    发明授权
    Inactivity triggered self clocking logic family 有权
    不活动触发自我计时逻辑家族

    公开(公告)号：US08575964B2

    公开(公告)日：2013-11-05

    申请号：US13426776

    申请日：2012-03-22

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966 ,  H03K19/0013

    摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY
    2.
    发明申请
    INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY 有权
    不活动触发自锁定逻辑系列

    公开(公告)号：US20130249596A1

    公开(公告)日：2013-09-26

    申请号：US13426776

    申请日：2012-03-22

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, JR. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, JR. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966 ,  H03K19/0013

    摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
    4.
    发明申请
    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS 有权
    优化低功率环境下计算效率的结构与方法

    公开(公告)号：US20090024859A1

    公开(公告)日：2009-01-22

    申请号：US11870575

    申请日：2007-10-11

    申请人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    发明人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    IPC分类号： G06F1/32

    CPC分类号： G06F1/26

    摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

    摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

    Structure and method to optimize computational efficiency in low-power environments
    5.
    发明授权
    Structure and method to optimize computational efficiency in low-power environments 有权
    在低功耗环境下优化计算效率的结构和方法

    公开(公告)号：US08122273B2

    公开(公告)日：2012-02-21

    申请号：US11870575

    申请日：2007-10-11

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/26

    摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

    摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

    Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereof
    6.
    发明授权
    Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereof 有权
    用于估计和/或预测功率周期长度的设计结构，估计和/或预测功率周期长度的方法及其电路

    公开(公告)号：US07903493B2

    公开(公告)日：2011-03-08

    申请号：US12109379

    申请日：2008-04-25

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： G11C5/14

    CPC分类号： G11C5/143

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded.

    摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括具有计数器，计数寄存器和非易失性存储器的阈值寄存器，用于当计数寄存器的值等于或超过阈值寄存器的值时存储状态。 还提供了一种预测和/或估计功率周期持续时间以便将状态保存在非易失性存储器和电路中的方法。 该方法包括设置阈值; 确定阈值已经相等或超过; 并且基于所述阈值相等或超过，在第一检查点处将所述状态保存在所述非易失性存储器中。

    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
    7.
    发明申请
    STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS 有权
    优化低功率环境下计算效率的结构与方法

    公开(公告)号：US20090024862A1

    公开(公告)日：2009-01-22

    申请号：US11779432

    申请日：2007-07-18

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    IPC分类号： G06F1/30

    CPC分类号： G06F1/3203

    摘要： A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.

    摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 该方法包括确定用于在低功率环境中最大化计算效率的最佳点，以及根据所确定的最佳点选择性地控制多个处理单元中的至少一个处理单元的操作。 该结构包括多个处理单元，控制多个处理单元中的至少一个处理单元的选择性并行操作的负载管理器和未调节的电源。

    Structure and method to optimize computational efficiency in low-power environments
    8.
    发明授权
    Structure and method to optimize computational efficiency in low-power environments 有权
    在低功耗环境下优化计算效率的结构和方法

    公开(公告)号：US08055925B2

    公开(公告)日：2011-11-08

    申请号：US11779432

    申请日：2007-07-18

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3203

    摘要： A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.

    摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 该方法包括确定用于在低功率环境中最大化计算效率的最佳点，以及根据确定的最佳点选择性地控制多个处理单元中的至少一个处理单元的操作。 该结构包括多个处理单元，控制多个处理单元中的至少一个处理单元的选择性并行操作的负载管理器和未调节的电源。

    Processor pipeline architecture logic state retention systems and methods
    9.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07937560B2

    公开(公告)日：2011-05-03

    申请号：US12121292

    申请日：2008-05-15

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

    摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。