Invention Grant
- Patent Title: Multi-chip stack structure
- Patent Title (中): 多芯片堆栈结构
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Application No.: US12968285Application Date: 2010-12-15
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Publication No.: US08581419B2Publication Date: 2013-11-12
- Inventor: Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
- Applicant: Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW99142393A 20101206
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.
Public/Granted literature
- US20120139092A1 MULTI-CHIP STACK STRUCTURE Public/Granted day:2012-06-07
Information query
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