公开(公告)号：US08581419B2

公开(公告)日：2013-11-12

申请号：US12968285

申请日：2010-12-15

Applicant: Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

Inventor： Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract translation: 提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。 第二芯片堆叠在第一芯片上。 第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。 屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。 屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。

公开(公告)号：US20130093454A1

公开(公告)日：2013-04-18

申请号：US13326331

申请日：2011-12-15

Applicant: Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

Inventor： Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

IPC: G01R31/26

CPC classification number: G01R31/318513 ,  G01R31/2812 ,  G01R31/31717 ,  H01L22/22

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract translation: 提供了设置在第一和第二芯片之间的通过硅通孔（TSV）的测试和修复设备。 第一和第二开关的第一端子耦合到TSV的第一端子。 第三和第四开关的第一端子耦合到TSV的第二端子。 第一电阻器的第一端子耦合到第一电压。 第一选择器耦合在第二开关的第二端子和第一电阻器之间。 第二选择器耦合在第四开关的第二端和第二电压之间。 第一控制电路检测第二开关的第二端子，并控制第一开关，第二开关和第一选择器。 第二控制电路控制第三开关，第四开关和第二选择器。

公开(公告)号：US09086455B2

公开(公告)日：2015-07-21

申请号：US13326331

申请日：2011-12-15

Applicant: Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

Inventor： Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

IPC: G01R31/02 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/317 ,  H01L21/66

CPC classification number: G01R31/318513 ,  G01R31/2812 ,  G01R31/31717 ,  H01L22/22

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract translation: 提供了设置在第一和第二芯片之间的通过硅通孔（TSV）的测试和修复设备。 第一和第二开关的第一端子耦合到TSV的第一端子。 第三和第四开关的第一端子耦合到TSV的第二端子。 第一电阻器的第一端子耦合到第一电压。 第一选择器耦合在第二开关的第二端子和第一电阻器之间。 第二选择器耦合在第四开关的第二端和第二电压之间。 第一控制电路检测第二开关的第二端子，并控制第一开关，第二开关和第一选择器。 第二控制电路控制第三开关，第四开关和第二选择器。

公开(公告)号：US20120139092A1

公开(公告)日：2012-06-07

申请号：US12968285

申请日：2010-12-15

Applicant: Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

Inventor： Keng-Li Su ,  Hsin-Chi Lai ,  Chih-Sheng Lin ,  Zhe-Hui Lin

IPC: H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract translation: 提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。 第二芯片堆叠在第一芯片上。 第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。 屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。 屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。