Invention Grant
- Patent Title: Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same
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Application No.: US13743012Application Date: 2013-01-16
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Publication No.: US08586475B2Publication Date: 2013-11-19
- Inventor: Hirokazu Sayama , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2002-336669 20021120
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
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