公开(公告)号：US09214464B2

公开(公告)日：2015-12-15

申请号：US14662276

申请日：2015-03-19

申请人： Renesas Electronics Corporation

发明人： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US09209191B2

公开(公告)日：2015-12-08

申请号：US14325570

申请日：2014-07-08

申请人： Renesas Electronics Corporation

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/44 ,  H01L27/108 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/66

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

摘要翻译： 用于形成nMOS晶体管的非绝缘硅栅极绝缘膜和栅电极设置在硅衬底上。 使用栅电极作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此栅极电极 非晶化 随后，提供氧化硅膜以覆盖栅电极，其温度小于栅电极发生再结晶的温度。 此后，在约1000℃的温度下进行热处理，由此在栅极上施加高的压缩残余应力，并且对栅电极下方的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US08987081B2

公开(公告)日：2015-03-24

申请号：US14481525

申请日：2014-09-09

申请人： Renesas Electronics Corporation

发明人： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20140377920A1

公开(公告)日：2014-12-25

申请号：US14481525

申请日：2014-09-09

申请人： Renesas Electronics Corporation

发明人： Kazunobu OTA ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

摘要翻译： 提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。 半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。 在低压NMOS区域（LNR）中的硅衬底（1）的表面中离子注入诸如砷的N型杂质，从而形成延伸层（61）。 然后，形成氧化硅膜（OX2）以覆盖硅衬底（1）的整个表面。 栅电极（51-54）侧面上的氧化硅膜（OX2）用作偏移侧壁。 然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对低的浓度，从而形成稍后为扩展层（62）的P型杂质层（621） 。

公开(公告)号：US08586475B2

公开(公告)日：2013-11-19

申请号：US13743012

申请日：2013-01-16

申请人： Renesas Electronics Corporation

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/44

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US11798886B2

公开(公告)日：2023-10-24

申请号：US17938497

申请日：2022-10-06

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hirokazu Sayama ,  Fumihiko Hayashi ,  Junjiro Sakai

IPC分类号： H01L23/535 ,  H01L21/74 ,  H01L21/762 ,  H01L21/764 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L21/764 ,  H01L21/76224

摘要： A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 μm.

公开(公告)号：US08642418B2

公开(公告)日：2014-02-04

申请号：US13964849

申请日：2013-08-12

申请人： Renesas Electronics Corporation

发明人： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L21/8238

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20130330890A1

公开(公告)日：2013-12-12

申请号：US13964849

申请日：2013-08-12

申请人： Renesas Electronics Corporation

发明人： Kazunobu OTA ,  Hirokazu Sayama ,  Hidekazu Oda

IPC分类号： H01L21/8238

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US09412867B2

公开(公告)日：2016-08-09

申请号：US14933079

申请日：2015-11-05

申请人： Renesas Electronics Corporation

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US08809186B2

公开(公告)日：2014-08-19

申请号：US14038981

申请日：2013-09-27

申请人： Renesas Electronics Corporation

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/44

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

摘要翻译： 用于形成nMOS晶体管的非绝缘硅栅极绝缘膜和栅电极设置在硅衬底上。 使用栅电极作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此栅极电极 非晶化 随后，提供氧化硅膜以覆盖栅电极，其温度小于栅电极发生再结晶的温度。 此后，在约1000℃的温度下进行热处理，由此在栅极上施加高的压缩残余应力，并且对栅电极下方的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。