- 专利标题: Analog floating gate charge loss compensation circuitry and method
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申请号: US13199002申请日: 2011-08-17
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公开(公告)号: US08593846B2公开(公告)日: 2013-11-26
- 发明人: David A. Helsley , Allan T. Mitchell
- 申请人: David A. Helsley , Allan T. Mitchell
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Alan A. R. Cooper; W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号: G11C27/00
- IPC分类号: G11C27/00
摘要:
An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.
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