公开(公告)号：US08593846B2

公开(公告)日：2013-11-26

申请号：US13199002

申请日：2011-08-17

申请人： David A. Helsley ,  Allan T. Mitchell

发明人： David A. Helsley ,  Allan T. Mitchell

IPC分类号： G11C27/00

CPC分类号： H03F3/45475 ,  H03F2203/45546 ,  H03F2203/45548

摘要： An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.

公开(公告)号：US08558296B2

公开(公告)日：2013-10-15

申请号：US13070222

申请日：2011-03-23

申请人： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

发明人： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/94 ,  G11C27/005 ,  G11C2216/10 ,  H01L27/1156 ,  H01L27/11803 ,  H01L28/40 ,  H01L28/60 ,  H01L29/7883 ,  H01L29/8616

摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

公开(公告)号：US20120313180A1

公开(公告)日：2012-12-13

申请号：US13569730

申请日：2012-08-08

申请人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC分类号： H01L21/8239 ,  H01L27/088

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

摘要： In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

摘要翻译： 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US5306935A

公开(公告)日：1994-04-26

申请号：US900225

申请日：1992-06-17

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551

摘要： A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

摘要翻译： 非易失性存储器阵列具有两个或多个层叠的存储器单元（10）。 底层可以包括平面的X电池或埋入的N ++ FAMOS晶体管阵列，并且顶层优选地包括平面晶体管阵列。 外延硅层（36）为第二层提供衬底。 堆叠层结构允许存储器密度增加两倍，而不缩放器件尺寸。

公开(公告)号：US5159570A

公开(公告)日：1992-10-27

申请号：US697228

申请日：1991-05-07

申请人： Allan T. Mitchell ,  Howard L. Tigelaar

发明人： Allan T. Mitchell ,  Howard L. Tigelaar

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/2815 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885 ,  H01L29/7887 ,  G11C2211/5612

摘要： An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.

摘要翻译： 公开了一种具有侧壁浮动栅极（28,28a，28b）的EEPROM存储单元。 侧壁浮动门（28,28a，28b）形成在中心块（22）的侧壁（30,32）上。 间隔开的位线（36,36a，36b）形成为用作存储器单元源和漏极。 侧壁浮动门（28a，28b）能够被彼此独立地编程。 当控制栅极（18）被启动并且位线（36a）或位线（36b）被用于读取器件时，可以根据侧壁浮动栅极（28a）或两者之一 ，28b）已被编程。

公开(公告)号：US5105245A

公开(公告)日：1992-04-14

申请号：US287937

申请日：1988-12-21

申请人： Bert R. Riemenschneider ,  Allan T. Mitchell ,  Clarence W. Teng

发明人： Bert R. Riemenschneider ,  Allan T. Mitchell ,  Clarence W. Teng

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

摘要翻译： 形成在（P-）外延层（11）和硅衬底（12）中的DRAM单元阵列的多个沟槽（26,28）和存储层（38,40）生长在侧壁 36）和底部（未示出）的沟槽（26,28）。 在沟槽（26,28）中形成高掺杂多晶硅电容器电极（42,44）。 形成侧壁氧化物细丝（50,54）和原位掺杂的侧壁导电细丝（66,68），并且使用热循环来将掺杂剂从侧壁导电细丝（66,68）扩散到上侧壁部分（62,64）中以形成 用于每个单元的通过栅极晶体管（90）的扩散源极区（70,72）。

公开(公告)号：US5084418A

公开(公告)日：1992-01-28

申请号：US465563

申请日：1990-01-16

申请人： Agerico L. Esquivel ,  Howard L. Tigelaar ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Howard L. Tigelaar ,  Allan T. Mitchell

IPC分类号： H01L21/74 ,  H01L23/535

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L2924/0002

摘要： Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.

摘要翻译： 位线（34）通过围绕沟槽（20）的侧壁和底部产生扩散区域（26）而形成。 沟槽（20）填充有导电区域（30），通常为难熔金属，难熔金属硅化物。

公开(公告)号：US5053839A

公开(公告)日：1991-10-01

申请号：US570944

申请日：1990-08-21

申请人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

IPC分类号： H01L27/115 ,  H01L29/08 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L29/0847

摘要： One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

摘要翻译： 本发明的一个实施例提供一种EPROM和一种制造具有增强的电容耦合的EPROM的方法。 每个沟槽的存储单元都包括褶状浮动栅极，其中控制栅极嵌套在浮动栅极的折叠中，以增加与控制栅极的耦合比。 因此，对于给定的编程电压，可以获得更高的编程速度和改善的单元密度。 沿着沟槽壁的位线的形成导致给定电池密度的较低的位线电阻率。

公开(公告)号：US4979005A

公开(公告)日：1990-12-18

申请号：US889454

申请日：1986-07-23

申请人： Allan T. Mitchell

发明人： Allan T. Mitchell

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/105 ,  H01L29/7885

摘要： A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

摘要翻译： 具有改进的掺杂分布的浮栅存储器单元。 在将衬底背景掺杂设置为期望水平（例如通过高剂量注入和长驱动）之后，使用相反类型的两个注入来形成浮栅晶体管的掺杂分布。 使用硼注入来在源/漏扩散的中点附近的深度处提供在通道下方的显着增加的p型掺杂。 浅砷植入物在表面部分地补偿该硼注入，以根据需要设定阈值电压。 大大增加的p型掺杂的区域有助于抑制否则可以抑制编程的横向寄生双极晶体管，并且（通过在漏极边界处提供增加的掺杂）增加热电子产生。

公开(公告)号：US4977439A

公开(公告)日：1990-12-11

申请号：US34305

申请日：1987-04-03

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/48 ,  H01L23/535

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L2924/0002

摘要： A method and apparatus for providing interconnections between levels on a semiconductor substrate of various types includes first forming a plurality of trenches in the substrate and then forming conductive layers at the bottom of the trenches. The trenches are then filled with an oxide to provide a planar surface on the substrate. Various levels of trenches are provided with crossovers being formed by a bridging layer of a conductive material that is formed over an oxide layer in the lower level trenches. Vertical contacts are formed by etching an opening from the surface to the bottom of the trenches through the oxide layer and filling the opening with a metal plug.

摘要翻译： 用于在各种类型的半导体衬底上提供电平之间的互连的方法和装置包括首先在衬底中形成多个沟槽，然后在沟槽的底部形成导电层。 然后用氧化物填充沟槽，以在衬底上提供平坦的表面。 提供了各种级别的沟槽，其中沟道由形成在下层沟槽中的氧化物层上的导电材料的桥接层形成。 通过蚀刻通过氧化物层从沟槽的表面到底部的开口并用金属插塞填充开口来形成垂直触点。