Invention Grant
- Patent Title: Cache memory power reduction techniques
- Patent Title (中): 高速缓存存储器功耗缩减技术
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Application No.: US12647461Application Date: 2009-12-26
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Publication No.: US08631207B2Publication Date: 2014-01-14
- Inventor: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
- Applicant: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
Public/Granted literature
- US20110161595A1 CACHE MEMORY POWER REDUCTION TECHNIQUES Public/Granted day:2011-06-30
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