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公开(公告)号:US08631207B2
公开(公告)日:2014-01-14
申请号:US12647461
申请日:2009-12-26
申请人: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号: G06F12/00
CPC分类号: G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译: 描述了提供存储器(诸如高速缓存存储器)中的功耗降低的方法和装置。 在一个实施例中,使用虚拟标签来确定是否访问缓存方式。 虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。 在另一个实施例中,可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。 还描述了其它实施例。
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公开(公告)号:US20110161595A1
公开(公告)日:2011-06-30
申请号:US12647461
申请日:2009-12-26
申请人: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
CPC分类号: G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译: 描述了提供存储器(诸如高速缓存存储器)中的功耗降低的方法和装置。 在一个实施例中,使用虚拟标签来确定是否访问缓存方式。 虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。 在另一个实施例中,可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。 还描述了其它实施例。
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公开(公告)号:US20120191896A1
公开(公告)日:2012-07-26
申请号:US13013104
申请日:2011-01-25
申请人: Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
发明人: Zhen Fang , Li Zhao , Ravishankar Iyer , Srihari Makineni , Guangdeng Liao
IPC分类号: G06F12/08
CPC分类号: G06F12/0813 , Y02D10/13
摘要: An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.
摘要翻译: 一个实施例可以包括至少部分地从多个存储器中选择至少一个存储器来存储数据的电路。 存储器可以与相应的处理器核心相关联。 该电路至少部分地至少部分地选择至少一个存储器,该至少一个存储器至少部分地基于是否将数据包括在跨越由至少一个处理器核处理的多个存储器线的至少一个页面中。 如果数据被包括在至少一个页面中,则电路可以至少部分地选择至少一个存储器,使得至少一个存储器靠近处理器核心中的至少一个。 许多替代方案,变化和修改是可能的。
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4.
公开(公告)号:US08621149B2
公开(公告)日:2013-12-31
申请号:US12645788
申请日:2009-12-23
申请人: Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
发明人: Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
CPC分类号: G06F12/0895 , G06F12/1491 , Y02D10/13
摘要: In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,高速缓冲存储器包括各自存储环电平标识符的条目,其可以指示存储在条目中的信息的权限级别。 该标识符可用于执行对高速缓冲存储器的读取访问。 作为示例,耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问, 更多的方式 描述和要求保护其他实施例。
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5.
公开(公告)号:US20110153926A1
公开(公告)日:2011-06-23
申请号:US12645788
申请日:2009-12-23
申请人: Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
发明人: Zhen Fang , Li Zhao , Ravishankar Iyer , Tong Li , Donald K. Newell
CPC分类号: G06F12/0895 , G06F12/1491 , Y02D10/13
摘要: In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,高速缓冲存储器包括各自存储环电平标识符的条目,其可以指示存储在条目中的信息的权限级别。 该标识符可用于执行对高速缓冲存储器的读取访问。 作为示例,耦合到高速缓存存储器的逻辑可以至少部分地基于处理器的当前特权级别和一个或多个高速缓冲存储器的环电平标识符来过滤对所选择的高速缓冲存储器组的一种或多种方式的访问, 更多的方式 描述和要求保护其他实施例。
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6.
公开(公告)号:US20100332788A1
公开(公告)日:2010-12-30
申请号:US12495509
申请日:2009-06-30
申请人: LI ZHAO , Zhen Fang , Ravishankar Iyer , Donald Newell
发明人: LI ZHAO , Zhen Fang , Ravishankar Iyer , Donald Newell
CPC分类号: G06F12/1027 , G06F2212/652
摘要: In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括页面错误处理程序,以响应于页面错误来创建页面表项和TLB条目,页面错误处理程序来确定页面错误是否由堆栈访问导致,以创建超级页面表项 页面错误确实来自堆栈访问,并为超级页面创建一个TLB条目。 描述和要求保护其他实施例。
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公开(公告)号:US08364862B2
公开(公告)日:2013-01-29
申请号:US12482614
申请日:2009-06-11
IPC分类号: G06F3/00
摘要: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于处理从主机处理器接收的注册消息的方法,其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。 来自消息的信息可以存储在轮询表中,并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。 描述和要求保护其他实施例。
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公开(公告)号:US09465751B2
公开(公告)日:2016-10-11
申请号:US13996438
申请日:2012-03-30
申请人: Xiaowei Jiang , Hongliang Gao , Zhen Fang , Srihari Makineni , Ravishankar Iyer
发明人: Xiaowei Jiang , Hongliang Gao , Zhen Fang , Srihari Makineni , Ravishankar Iyer
CPC分类号: G06F12/1466 , G06F12/1027 , G06F12/126
摘要: An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
摘要翻译: 描述了一种装置,其包含处理核心,其包括CPU核心和耦合到CPU核心的至少一个加速器。 CPU核心包括具有翻译旁边缓冲器的管线。 CPU核心包括逻辑电路,用于在转换后备缓冲器条目中的条目的属性数据中设置锁定位,以锁定为加速器保留的存储器页面。
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公开(公告)号:US08819388B2
公开(公告)日:2014-08-26
申请号:US13550966
申请日:2012-07-17
申请人: Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E. Espig , Ravishankar Iyer
发明人: Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E. Espig , Ravishankar Iyer
CPC分类号: G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
摘要: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
摘要翻译: 描述了用于控制片上系统结构(OSF)块的方法和装置。 在一个实施例中,响应于用户级请求可以存储对应于物理地址的影子地址,并且逻辑电路(例如,存在于OSF中)可以从影子地址确定物理地址。 还公开了其他实施例。
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公开(公告)号:US08412885B2
公开(公告)日:2013-04-02
申请号:US12590651
申请日:2009-11-12
申请人: Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
发明人: Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
IPC分类号: G06F12/00
CPC分类号: G06F12/0895 , Y02D10/13
摘要: In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.
摘要翻译: 在本发明的实施例中,一种方法包括:向存储器控制器发送数据请求; 按重要性或优先次序安排数据请求; 识别数据请求的来源; 并且如果源是输入/输出设备,则遮蔽高速缓存中的P路; 并分配填充缓存的方法。 描述和要求保护其他实施例。
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