Invention Grant
- Patent Title: Method of manufacturing chip-stacked semiconductor package
- Patent Title (中): 芯片堆叠半导体封装的制造方法
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Application No.: US13439447Application Date: 2012-04-04
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Publication No.: US08637350B2Publication Date: 2014-01-28
- Inventor: Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
- Applicant: Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
- Applicant Address: KR Suwon-Si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2011-0041543 20110502
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
Public/Granted literature
- US20120282735A1 METHOD OF MANUFACTURING CHIP-STACKED SEMICONDUCTOR PACKAGE Public/Granted day:2012-11-08
Information query
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