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公开(公告)号：US08637350B2
公开(公告)日：2014-01-28
申请号：US13439447
申请日：2012-04-04
Applicant: Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
Inventor： Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
IPC: H01L21/00
CPC classification number: H01L25/50 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3192 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2221/68381 , H01L2224/0346 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11009 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/2929 , H01L2224/29387 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83191 , H01L2224/83192 , H01L2224/83851 , H01L2224/92125 , H01L2224/92143 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06568 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。
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2.发明申请SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES 有权通过电极和通过电极互连的堆叠半导体芯片的半导体芯片公开(公告)号：US20120299194A1
公开(公告)日：2012-11-29
申请号：US13569653
申请日：2012-08-08
Applicant: Ho-jin Lee , Hyun-soo Chung , Chang-seong Jeon , Sang-sick Park , Jae-hyun Phee
Inventor： Ho-jin Lee , Hyun-soo Chung , Chang-seong Jeon , Sang-sick Park , Jae-hyun Phee
IPC: H01L23/48
CPC classification number: H01L23/48 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01327 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/04953 , H01L2924/04941
Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.
Abstract translation: 半导体器件包括半导体衬底和通孔电极。 通孔电极在基板上具有第一部分并且朝向基板延伸并且具有从第一部分延伸到基板中的多个尖峰，每个尖峰彼此间隔开。
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3.发明申请PROBE CARD HAVING REDISTRIBUTED WIRING PROBE NEEDLE STRUCTURE AND PROBE CARD MODULE USING THE SAME 审中-公开具有重新配置的接线探针结构的探针卡和使用其的探针卡模块公开(公告)号：US20090278561A1
公开(公告)日：2009-11-12
申请号：US12330146
申请日：2008-12-08
Applicant: Cha-jea Jo , Tae-gyeong Chung , Hoon-jung Kim , Nam-seog Kim , Chang-seong Jeon
Inventor： Cha-jea Jo , Tae-gyeong Chung , Hoon-jung Kim , Nam-seog Kim , Chang-seong Jeon
IPC: G01R1/073
CPC classification number: G01R31/2889 , G01R1/06716 , G01R1/06733
Abstract: The probe card is comprised of a probe card wafer, a plurality of through via electrodes penetrating the probe card wafer; and a plurality of redistributed wiring probe needle structures, each being connected to the through via electrodes protruding from a surface of the probe card wafer.
Abstract translation: 探针卡由探针卡晶片，穿过探针卡晶片的多个通孔电极组成; 以及多个重新分布的布线探针针结构，每个连接到从探针卡晶片的表面突出的通孔电极。
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4.发明申请FABRICATING METHODS OF SEMICONDUCTOR DEVICES AND PICK-UP APPARATUSES OF SEMICONDUCTOR DEVICES THEREIN 审中-公开半导体器件的制造方法及其半导体器件的拾取器件公开(公告)号：US20130149817A1
公开(公告)日：2013-06-13
申请号：US13559141
申请日：2012-07-26
Applicant: Chang-Seong JEON , Sang-Sick PARK , Sang-Wook PARK , Teak-Hoon LEE , Kwang-Chul CHOI
Inventor： Chang-Seong JEON , Sang-Sick PARK , Sang-Wook PARK , Teak-Hoon LEE , Kwang-Chul CHOI
IPC: H01L21/762
CPC classification number: H01L21/67144 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/50 , H01L2224/13101 , H01L2224/16145 , H01L2224/75822 , H01L2224/75823 , H01L2224/8117 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/014 , H01L2924/00014
Abstract: A fabricating method of a semiconductor device may include forming a semiconductor die on a supporting wafer, and picking up the die from the wafer by attaching to the die a transfer unit, the transfer unit including a head unit configured to enable twisting movement, and performing the twisting movement. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer; and picking up the first semiconductor device from the wafer, moving the first semiconductor device onto a second semiconductor device, and bonding the first semiconductor device to the second semiconductor device while maintaining the first semiconductor device oriented so that a surface faces upwardly. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer, attaching to the first semiconductor device a transfer unit configured to enable twisting movement, and performing the twisting movement.
Abstract translation: 半导体器件的制造方法可以包括在支撑晶片上形成半导体管芯，并且通过将转移单元附接到管芯而从晶片上拾取管芯，所述转移单元包括构造成能够进行扭转运动的头单元，以及执行 扭转运动。 半导体器件的制造方法可以包括在支撑晶片上形成第一半导体器件; 以及从所述晶片拾取所述第一半导体器件，将所述第一半导体器件移动到第二半导体器件上，并且将所述第一半导体器件接合到所述第二半导体器件，同时保持所述第一半导体器件定向成使得表面朝上。 半导体器件的制造方法可以包括在支撑晶片上形成第一半导体器件，附接到第一半导体器件，被配置为能够进行扭转运动并执行扭转运动的转移单元。
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公开(公告)号：US09461029B2
公开(公告)日：2016-10-04
申请号：US14744031
申请日：2015-06-19
Applicant: Hye-young Jang , Chang-Seong Jeon , Chajea Jo , Taeje Cho
Inventor： Hye-young Jang , Chang-Seong Jeon , Chajea Jo , Taeje Cho
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/1412 , H01L2224/1413 , H01L2224/16146 , H01L2224/16227 , H01L2224/17104 , H01L2224/2919 , H01L2224/32013 , H01L2224/321 , H01L2224/32145 , H01L2224/33181 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83203 , H01L2224/83379 , H01L2224/92 , H01L2224/9211 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2924/1434 , H01L2924/15311 , H01L2924/18161 , H01L2924/181 , H01L2924/00012 , H01L2924/014
Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
Abstract translation: 半导体封装可以包括第一半导体芯片，其包括面向封装基板的第一表面，与第一表面相对的第二表面，以及穿透第一半导体芯片的至少一个贯通电极，模制第一半导体芯片的模制层和暴露 第一半导体芯片的第二表面，堆叠在第一半导体芯片的第二表面上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的非导电膜。 第二半导体芯片包括延伸穿过第一半导体芯片的边缘的突出部分。 例如，第二半导体芯片的尺寸可以大于第一半导体芯片的尺寸，因此第二半导体芯片具有突出端。 第二半导体芯片包括电连接到至少一个通孔的至少一个互连端子。
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Patent Agency Ranking
公开(公告)号：US20150380394A1
公开(公告)日：2015-12-31
申请号：US14744031
申请日：2015-06-19
Applicant: Hye-young JANG , Chang-Seong JEON , CHAJEA JO , Taeje CHO
Inventor： Hye-young JANG , Chang-Seong JEON , CHAJEA JO , Taeje CHO
IPC: H01L25/00 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/18
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/1412 , H01L2224/1413 , H01L2224/16146 , H01L2224/16227 , H01L2224/17104 , H01L2224/2919 , H01L2224/32013 , H01L2224/321 , H01L2224/32145 , H01L2224/33181 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83203 , H01L2224/83379 , H01L2224/92 , H01L2224/9211 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2924/1434 , H01L2924/15311 , H01L2924/18161 , H01L2924/181 , H01L2924/00012 , H01L2924/014
Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
Abstract translation: 半导体封装可以包括第一半导体芯片，其包括面向封装基板的第一表面，与第一表面相对的第二表面，以及穿透第一半导体芯片的至少一个贯通电极，模制第一半导体芯片的模制层和暴露 第一半导体芯片的第二表面，堆叠在第一半导体芯片的第二表面上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的非导电膜。 第二半导体芯片包括延伸穿过第一半导体芯片的边缘的突出部分。 例如，第二半导体芯片的尺寸可以大于第一半导体芯片的尺寸，因此第二半导体芯片具有突出端。 第二半导体芯片包括电连接到至少一个通孔的至少一个互连端子。
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公开(公告)号：US20140154839A1
公开(公告)日：2014-06-05
申请号：US14093853
申请日：2013-12-02
Applicant: Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
Inventor： Jung-seok Ahn , Dong-hyeon Jang , Ho-geon Song , Sung-jun Im , Chang-seong Jeon , Teak-hoon Lee , Sang-sick Park
IPC: H01L25/00
CPC classification number: H01L25/50 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3192 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2221/68381 , H01L2224/0346 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11009 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/2929 , H01L2224/29387 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83191 , H01L2224/83192 , H01L2224/83851 , H01L2224/92125 , H01L2224/92143 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06568 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。
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8.发明授权Method of manufacturing a flip chip package and apparatus to attach a semiconductor chip used in the method 有权制造倒装芯片封装的方法和用于附接在该方法中使用的半导体芯片的装置公开(公告)号：US08697494B2
公开(公告)日：2014-04-15
申请号：US13241517
申请日：2011-09-23
Applicant: Chang-Seong Jeon , Ho-Geon Song , Mitsuo Umemoto , Sang-Sick Park
Inventor： Chang-Seong Jeon , Ho-Geon Song , Mitsuo Umemoto , Sang-Sick Park
IPC: H01L21/00
CPC classification number: H01L24/74 , H01L21/67 , H01L23/16 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32151 , H01L2224/32225 , H01L2224/73204 , H01L2224/7501 , H01L2224/7515 , H01L2224/7525 , H01L2224/75252 , H01L2224/75804 , H01L2224/75824 , H01L2224/759 , H01L2224/7598 , H01L2224/7901 , H01L2224/81011 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2224/8385 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , Y10T29/53178 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.
Abstract translation: 制造倒装芯片封装的方法和装置包括将焊剂点到封装衬底的第一预备凸块上，通过焊剂将第一半导体芯片的初步凸点附着到封装衬底的第一初步凸块上，点焊焊剂 封装衬底的第二初步凸块，以及通过焊剂将第二半导体芯片的预备凸块附接到封装衬底的第二初级凸块。 因此，可以抑制在封装衬底的初步凸块上的焊剂的蒸发。
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9.发明申请公开(公告)号：US20120313332A1
公开(公告)日：2012-12-13
申请号：US13495837
申请日：2012-06-13
Applicant: Chang-Seong Jeon , Sangwook Park , TeakHoon Lee , Ilyoung Han
Inventor： Chang-Seong Jeon , Sangwook Park , TeakHoon Lee , Ilyoung Han
IPC: H01L21/683
CPC classification number: H01L21/6838 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/73104 , H01L2224/75315 , H01L2224/75745 , H01L2224/7598 , H01L2224/94 , H01L2224/97 , H01L2924/01006 , H01L2924/014 , Y10T279/11 , H01L2224/81
Abstract: Apparatuses of manufacturing semiconductor packages are provided. An apparatus includes a chuck having a body, a porous plate disposed on the body, and a buffer pad disposed on the plate to provide a place on which a plurality of chips are loaded. The buffer pad has elasticity greater than the plate. The apparatus also includes a vacuum part supplying vacuum to the chuck so that the plurality of chips are sucked onto the buffer pad. Methods of manufacturing semiconductor packages using the apparatus are also provided.
Abstract translation: 提供制造半导体封装的装置。 一种装置包括具有主体的卡盘，设置在主体上的多孔板，以及设置在板上的缓冲垫，以提供加载有多个芯片的位置。 缓冲垫具有大于板的弹性。 该装置还包括一个向卡盘提供真空的真空部分，使得多个芯片被吸到缓冲垫上。 还提供了使用该装置制造半导体封装的方法。
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10.发明申请METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND APPARATUS TO ATTACH A SEMICONDUCTOR CHIP USED IN THE METHOD 有权制造片状芯片包装的方法和装置，以附加在方法中使用的半导体芯片公开(公告)号：US20120100668A1
公开(公告)日：2012-04-26
申请号：US13241517
申请日：2011-09-23
Applicant: Chang-Seong Jeon , Ho-Geon Song , Mitsuo Umemoto , Sang-Sick Park
Inventor： Chang-Seong Jeon , Ho-Geon Song , Mitsuo Umemoto , Sang-Sick Park
CPC classification number: H01L24/74 , H01L21/67 , H01L23/16 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32151 , H01L2224/32225 , H01L2224/73204 , H01L2224/7501 , H01L2224/7515 , H01L2224/7525 , H01L2224/75252 , H01L2224/75804 , H01L2224/75824 , H01L2224/759 , H01L2224/7598 , H01L2224/7901 , H01L2224/81011 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2224/8385 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , Y10T29/53178 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.
Abstract translation: 制造倒装芯片封装的方法和装置包括将焊剂点到封装衬底的第一预备凸块上，通过焊剂将第一半导体芯片的初步凸点附着到封装衬底的第一初步凸块上，点焊焊剂 封装衬底的第二初步凸块，以及通过焊剂将第二半导体芯片的预备凸块附接到封装衬底的第二初级凸块。 因此，可以抑制在封装衬底的初步凸块上的焊剂的蒸发。
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